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Re: [Qemu-devel] [PATCH] tcg/ppc64: Fix zero extension code generation b
From: |
Alexander Graf |
Subject: |
Re: [Qemu-devel] [PATCH] tcg/ppc64: Fix zero extension code generation bug for ppc64 host |
Date: |
Fri, 9 Sep 2011 11:31:37 +0200 |
On 09.09.2011, at 07:58, David Gibson wrote:
> From: Thomas Huth <address@hidden>
>
> The ppc64 code generation backend uses an rldicr (Rotate Left Double
> Immediate and Clear Right) instruction to implement zero extension of
> a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64). However
> this is wrong - this instruction clears specified low bits of the
> value, instead of high bits as we require for a zero extension. It
> should instead use an rldicl (Rotate Left Double Immediate and Clear
> Left) instruction.
>
> Presumably amongst other things, this causes the SLOF firmware image
> used with -M pseries to not boot on a ppc64 host.
>
> It appears this bug was exposed by commit
> 0bf1dbdcc935dfc220a93cd990e947e90706aec6 (tcg/ppc64: fix 16/32 mixup)
> which enabled the use of the op_ext32u_i64 operation on the ppc64
> backend.
Very nice! Let's ask Andreas and/or malc to take care of it though :)
Alex
>
> Signed-off-by: Thomas Huth <address@hidden>
> Signed-off-by: David Gibson <address@hidden>
> ---
> tcg/ppc64/tcg-target.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
> index d831684..e3c63ad 100644
> --- a/tcg/ppc64/tcg-target.c
> +++ b/tcg/ppc64/tcg-target.c
> @@ -1560,7 +1560,7 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
> const TCGArg *args,
> break;
>
> case INDEX_op_ext32u_i64:
> - tcg_out_rld (s, RLDICR, args[0], args[1], 0, 32);
> + tcg_out_rld (s, RLDICL, args[0], args[1], 0, 32);
> break;
>
> case INDEX_op_setcond_i32:
> --
> 1.7.5.4
>