[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank |
Date: |
Fri, 6 Jan 2012 17:04:12 +0000 |
On 6 January 2012 16:58, Mark Langsdorf <address@hidden> wrote:
> On 01/06/2012 10:29 AM, Peter Maydell wrote:
>>> + /* Override default RAM size */
>>> + if (ram_size == 0x8000000) {
>>> + if (sizeof(long) == 8) {
>>> + ram_size = 0xff900000;
>>> + } else {
>>> + ram_size = 0x80000000;
>>> + }
>>
>> Yuck. Model behaviour shouldn't depend on properties of
>> the host system like sizeof(long).
>
> The board is populated with 4G of DRAM, which we'd like
> to support if the host can. Is there a better way to do
> that?
Don't mess with the default, have the user specify a RAM size that
makes sense for their host machine. It's not fantastic but it's what
QEMU has at the moment.
I once tried to suggest a patchset which would allow boards to
specify their min/max/default RAM sizes but it got shot down.
>>> + sysmem = get_system_memory();
>>> + dram = g_new(MemoryRegion, 1);
>>> + memory_region_init_ram(dram, "highbank.dram", ram_size);
>>> + /* SDRAM at address zero. */
>>> + memory_region_add_subregion(sysmem, 0, dram);
>>> +
>>> + sysram = g_new(MemoryRegion, 1);
>>> + memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
>>> + memory_region_add_subregion(sysmem, 0xfff88000, sysram);
>>> + if (load_image_targphys("sysram.bin", 0xfff88000, 0x8000) < 0) {
>>> + fprintf(stderr, "Unable to load sysram.bin\n");
>>> + }
>>
>> Is this for some sort of BIOS-image equivalent?
>
> Yes, uboot and the like. It isn't necessary to boot the system,
> but it models the actual board a bit better.
If it's not necessary, should we be failing if there isn't an image file
present?
-- PMM
- [Qemu-devel] [PATCH 0/5] arm: add support for Calxeda Highbank SoC, Mark Langsdorf, 2012/01/05
- [Qemu-devel] [PATCH 3/5] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2012/01/05
- [Qemu-devel] [PATCH v5 2/5] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2012/01/05
- [Qemu-devel] [PATCH v5 1/5] Add xgmac ethernet model, Mark Langsdorf, 2012/01/05
- [Qemu-devel] [PATCH 4/5] arm: Add dummy support for co-processor 15's secure config register, Mark Langsdorf, 2012/01/05
- [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/05
- Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank, Mark Langsdorf, 2012/01/06
- Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank, Peter Maydell, 2012/01/06
Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank, Andreas Färber, 2012/01/06
Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank, Igor Mitsyanko, 2012/01/06