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From: | Igor Mitsyanko |
Subject: | Re: [Qemu-devel] [PATCH 5/5] arm: SoC model for Calxeda Highbank |
Date: | Fri, 06 Jan 2012 22:37:18 +0400 |
User-agent: | Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.2.24) Gecko/20111108 Thunderbird/3.1.16 |
On 01/06/2012 12:02 AM, Mark Langsdorf wrote:Hello, Mark. According to technical specification on Calxeda website, highbank SoC has SD 3.0 host controller, are you planning to implement it in qemu? I'm asking because I recently have submitted a patch implementing SD 2.0 host controller, and it looks like these two specifications revisions are not very different from each other.
+ if (!cpu_model) { + cpu_model = "cortex-a9"; + }
Google said there is only cortexA9-based Highbank SoC version, maybe you should just hardcode cpu model?
+ /* Override default RAM size */ + if (ram_size == 0x8000000) { + if (sizeof(long) == 8) { + ram_size = 0xff900000; + } else {
This value looks a bit strange, usually DRAM consists of several banks 512, 256 (or something like that) megabytes each, I couldn't find what DRAM configuration does the actual board have?
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