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[Qemu-devel] [RFC 1/9] target-xtensa: add DEBUGCAUSE SR and configuratio
From: |
Max Filippov |
Subject: |
[Qemu-devel] [RFC 1/9] target-xtensa: add DEBUGCAUSE SR and configuration |
Date: |
Sun, 29 Jan 2012 06:19:23 +0400 |
DEBUGCAUSE SR holds information about the most recent debug exception.
See ISA, 4.7.7 for more details.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/cpu.h | 15 +++++++++++++++
target-xtensa/translate.c | 6 ++++++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 0db83a6..25245d8 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -137,6 +137,7 @@ enum {
PS = 230,
VECBASE = 231,
EXCCAUSE = 232,
+ DEBUGCAUSE = 233,
CCOUNT = 234,
PRID = 235,
EXCVADDR = 238,
@@ -161,6 +162,15 @@ enum {
#define PS_WOE 0x40000
+#define DEBUGCAUSE_IC 0x1
+#define DEBUGCAUSE_IB 0x2
+#define DEBUGCAUSE_DB 0x4
+#define DEBUGCAUSE_BI 0x8
+#define DEBUGCAUSE_BN 0x10
+#define DEBUGCAUSE_DI 0x20
+#define DEBUGCAUSE_DBNUM 0xf00
+#define DEBUGCAUSE_DBNUM_SHIFT 8
+
#define MAX_NAREG 64
#define MAX_NINTERRUPT 32
#define MAX_NLEVEL 6
@@ -279,6 +289,11 @@ typedef struct XtensaConfig {
uint32_t timerint[MAX_NCCOMPARE];
unsigned nextint;
unsigned extint[MAX_NINTERRUPT];
+
+ unsigned debug_level;
+ unsigned nibreak;
+ unsigned ndbreak;
+
uint32_t clock_freq_khz;
xtensa_tlb itlb;
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index c81450d..0786dd1 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -119,6 +119,7 @@ static const char * const sregnames[256] = {
[PS] = "PS",
[VECBASE] = "VECBASE",
[EXCCAUSE] = "EXCCAUSE",
+ [DEBUGCAUSE] = "DEBUGCAUSE",
[CCOUNT] = "CCOUNT",
[PRID] = "PRID",
[EXCVADDR] = "EXCVADDR",
@@ -535,6 +536,10 @@ static void gen_wsr_ps(DisasContext *dc, uint32_t sr,
TCGv_i32 v)
gen_jumpi_check_loop_end(dc, -1);
}
+static void gen_wsr_debugcause(DisasContext *dc, uint32_t sr, TCGv_i32 v)
+{
+}
+
static void gen_wsr_prid(DisasContext *dc, uint32_t sr, TCGv_i32 v)
{
}
@@ -571,6 +576,7 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32
s)
[INTCLEAR] = gen_wsr_intclear,
[INTENABLE] = gen_wsr_intenable,
[PS] = gen_wsr_ps,
+ [DEBUGCAUSE] = gen_wsr_debugcause,
[PRID] = gen_wsr_prid,
[CCOMPARE] = gen_wsr_ccompare,
[CCOMPARE + 1] = gen_wsr_ccompare,
--
1.7.7.6
- [Qemu-devel] [RFC 0/9] target-xtensa: implement debug option, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 1/9] target-xtensa: add DEBUGCAUSE SR and configuration,
Max Filippov <=
- [Qemu-devel] [RFC 2/9] target-xtensa: implement instruction breakpoints, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 3/9] target-xtensa: add ICOUNT SR and debug exception, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 5/9] exec: fix check_watchpoint exiting cpu_loop, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 6/9] exec: let cpu_watchpoint_insert accept larger watchpoints, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 4/9] exec: add missing breaks to the watch_mem_write, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 8/9] target-xtensa: add DEBUG_SECTION to overlay tool, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 7/9] target-xtensa: add DBREAK data breakpoints, Max Filippov, 2012/01/28
- [Qemu-devel] [RFC 9/9] target-xtensa: add breakpoint tests, Max Filippov, 2012/01/28