[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3 |
Date: |
Tue, 19 Feb 2013 09:40:09 -0800 |
From: Paolo Bonzini <address@hidden>
It is almost unused, and it is simpler to pass a TCG value directly
to gen_shiftd_rm_T1_T3. This value is then written to t2 without
going through a temporary register.
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9d5467d..60c1fdd 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -64,7 +64,7 @@ static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst;
static TCGv_i32 cpu_cc_op;
static TCGv cpu_regs[CPU_NB_REGS];
/* local temps */
-static TCGv cpu_T[2], cpu_T3;
+static TCGv cpu_T[2];
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0, cpu_tmp4;
static TCGv_ptr cpu_ptr0, cpu_ptr1;
@@ -1858,8 +1858,8 @@ static void gen_rotc_rm_T1(DisasContext *s, int ot, int
op1,
}
/* XXX: add faster immediate case */
-static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
- int is_right)
+static void gen_shiftd_rm_T1(DisasContext *s, int ot, int op1,
+ int is_right, TCGv count)
{
int label1, label2, data_bits;
target_ulong mask;
@@ -1883,10 +1883,8 @@ static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot,
int op1,
gen_op_mov_v_reg(ot, t0, op1);
}
- tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
-
+ tcg_gen_andi_tl(t2, count, mask);
tcg_gen_mov_tl(t1, cpu_T[1]);
- tcg_gen_mov_tl(t2, cpu_T3);
/* Must test zero case to avoid using undefined behaviour in TCG
shifts. */
@@ -5583,12 +5581,12 @@ static target_ulong disas_insn(CPUX86State *env,
DisasContext *s,
gen_op_mov_TN_reg(ot, 1, reg);
if (shift) {
- val = cpu_ldub_code(env, s->pc++);
- tcg_gen_movi_tl(cpu_T3, val);
+ TCGv imm = tcg_const_tl(cpu_ldub_code(env, s->pc++));
+ gen_shiftd_rm_T1(s, ot, opreg, op, imm);
+ tcg_temp_free(imm);
} else {
- tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
+ gen_shiftd_rm_T1(s, ot, opreg, op, cpu_regs[R_ECX]);
}
- gen_shiftd_rm_T1_T3(s, ot, opreg, op);
break;
/************************/
@@ -7869,7 +7867,6 @@ static inline void
gen_intermediate_code_internal(CPUX86State *env,
cpu_T[0] = tcg_temp_new();
cpu_T[1] = tcg_temp_new();
cpu_A0 = tcg_temp_new();
- cpu_T3 = tcg_temp_new();
cpu_tmp0 = tcg_temp_new();
cpu_tmp1_i64 = tcg_temp_new_i64();
--
1.8.1.2
- [Qemu-devel] [PATCH 44/57] target-i386: Decode the VEX prefixes, (continued)
- [Qemu-devel] [PATCH 44/57] target-i386: Decode the VEX prefixes, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 40/57] target-i386: Don't reference ENV through most of cc helpers, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 43/57] target-i386: Tidy prefix parsing, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 08/57] target-i386: move eflags computation closer to gen_op_set_cc_op, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 48/57] target-i386: Implement BLSR, BLSMSK, BLSI, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 45/57] target-i386: Implement MOVBE, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 32/57] target-i386: cleanup temporary macros for CCPrepare, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 47/57] target-i386: Implement BEXTR, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 27/57] target-i386: optimize setcc instructions, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 19/57] target-i386: no need to flush out cc_op before gen_eob, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3,
Richard Henderson <=
- [Qemu-devel] [PATCH 50/57] target-i386: Implement MULX, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 09/57] target-i386: compute eflags outside rcl/rcr helper, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 06/57] target-i386: drop cc_op argument of gen_jcc1, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 54/57] target-i386: Implement ADX extension, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 20/57] target-i386: Move CC discards to set_cc_op, Richard Henderson, 2013/02/19
- Re: [Qemu-devel] [PATCH v3 00/57] target-i386 flags improvements and bmi/adx extensions, Paolo Bonzini, 2013/02/19
- [Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 12/57] target-i386: factor gen_op_set_cc_op/tcg_gen_discard_tl around computing flags, Richard Henderson, 2013/02/19