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[Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond |
Date: |
Tue, 19 Feb 2013 09:40:08 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/translate.c | 45 ++++++++++++++++++++-------------------------
1 file changed, 20 insertions(+), 25 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 4b0a701..9d5467d 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2417,35 +2417,30 @@ static inline void gen_jcc(DisasContext *s, int b,
static void gen_cmovcc1(CPUX86State *env, DisasContext *s, int ot, int b,
int modrm, int reg)
{
- int l1, mod = (modrm >> 6) & 3;
- TCGv t0 = tcg_temp_local_new();
+ CCPrepare cc;
- if (mod != 3) {
- int reg_addr, offset_addr;
- gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
- gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
- } else {
- int rm = (modrm & 7) | REX_B(s);
- gen_op_mov_v_reg(ot, t0, rm);
- }
+ gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
- l1 = gen_new_label();
- gen_jcc1(s, b ^ 1, l1);
- switch (ot) {
-#ifdef TARGET_X86_64
- case OT_LONG:
- tcg_gen_mov_tl(cpu_regs[reg], t0);
- gen_set_label(l1);
- tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
- break;
-#endif
- default:
- gen_op_mov_reg_v(ot, reg, t0);
- gen_set_label(l1);
- break;
+ cc = gen_prepare_cc(s, b, cpu_T[1]);
+ if (cc.mask != -1) {
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, cc.reg, cc.mask);
+ cc.reg = t0;
+ }
+ if (!cc.use_reg2) {
+ cc.reg2 = tcg_const_tl(cc.imm);
}
- tcg_temp_free(t0);
+ tcg_gen_movcond_tl(cc.cond, cpu_T[0], cc.reg, cc.reg2,
+ cpu_T[0], cpu_regs[reg]);
+ gen_op_mov_reg_T0(ot, reg);
+
+ if (cc.mask != -1) {
+ tcg_temp_free(cc.reg);
+ }
+ if (!cc.use_reg2) {
+ tcg_temp_free(cc.reg2);
+ }
}
static inline void gen_op_movl_T0_seg(int seg_reg)
--
1.8.1.2
- Re: [Qemu-devel] [PATCH 54/57] target-i386: Implement ADX extension, (continued)
- [Qemu-devel] [PATCH 20/57] target-i386: Move CC discards to set_cc_op, Richard Henderson, 2013/02/19
- Re: [Qemu-devel] [PATCH v3 00/57] target-i386 flags improvements and bmi/adx extensions, Paolo Bonzini, 2013/02/19
- [Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 12/57] target-i386: factor gen_op_set_cc_op/tcg_gen_discard_tl around computing flags, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 14/57] target-i386: Introduce set_cc_op, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 55/57] target-i386: Use clz/ctz for bsf/bsr helpers, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 10/57] target-i386: clean up sahf, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 13/57] target-i386: Name the cc_op enumeration, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 11/57] target-i386: use gen_jcc1 to compile loopz, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond,
Richard Henderson <=
- [Qemu-devel] [PATCH 07/57] target-i386: move carry computation for inc/dec closer to gen_op_set_cc_op, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 57/57] target-i386: Add CC_OP_CLR, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 29/57] target-i386: introduce gen_prepare_cc, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 21/57] target-i386: do not call helper to compute ZF/SF, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 53/57] target-i386: Implement RORX, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 15/57] target-i386: Don't clobber s->cc_op in gen_update_cc_op, Richard Henderson, 2013/02/19