[Qemu-devel] [PATCH 00/10] target-i386: fix and enable SSE4.1 and SSE4.2

[Aurelien Jarno]

SSE4.1 and SSE4.2 instruction sets are partly broken, at least enough to
render a recent glibc with ifunc enabled unusable.

This patch series fixes the issues, it has been tested with the valgrind
testsuite in user mode and by booting x86 and x86-64 guests with a
recent glibc in system mode. 

Aurelien Jarno (10):
  target-i386: SSE4.1: fix pinsrb instruction
  target-i386: SSE4.2: fix pcmpgtq instruction
  target-i386: SSE4.2: fix pcmpXstri instructions
  target-i386: SSE4.2: fix pcmpXstrm instructions
  target-i386: SSE4.2: fix pcmpXstrX instructions in "Ranges" mode
  target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal each" mode
  target-i386: SSE4.2: fix pcmpXstrX instructions in "Equal ordered" mode
  target-i386: SSE4.2: fix pcmpXstrX instructions with "Masked(-)" polarity
  target-i386: enable SSE4.1 and SSE4.2 in TCG mode
  target-i386: SSE4.2: use clz32/ctz32 instead of reinventing the wheel

 target-i386/cpu.c        |   13 +++++-----
 target-i386/fpu_helper.c |    1 +
 target-i386/ops_sse.h    |   64 +++++++++++++---------------------------------
 target-i386/translate.c  |    4 +--
 4 files changed, 28 insertions(+), 54 deletions(-)

-- 
1.7.10.4