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[Qemu-devel] [PATCH] target-mips: set carry bit correctly in DSPControl
From: |
Petar Jovanovic |
Subject: |
[Qemu-devel] [PATCH] target-mips: set carry bit correctly in DSPControl register |
Date: |
Mon, 13 May 2013 17:14:35 +0200 |
From: Petar Jovanovic <address@hidden>
First we need to clear the bit and then we set the given value.
Instruction ADDSC sets the bit and instruction ADDWC uses this bit.
Signed-off-by: Petar Jovanovic <address@hidden>
---
target-mips/dsp_helper.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index 9212789..e98bac8 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -53,9 +53,10 @@ static inline void set_DSPControl_overflow_flag(uint32_t
flag, int position,
env->active_tc.DSPControl |= (target_ulong)flag << position;
}
-static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
+static inline void set_DSPControl_carryflag(bool flag, CPUMIPSState *env)
{
- env->active_tc.DSPControl |= (target_ulong)flag << 13;
+ env->active_tc.DSPControl &= ~(1 << 13);
+ env->active_tc.DSPControl |= flag << 13;
}
static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
@@ -1266,7 +1267,7 @@ SUBUH_QB(subuh_r, 1);
target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
{
uint64_t temp, tempRs, tempRt;
- int32_t flag;
+ bool flag;
tempRs = (uint64_t)rs & MIPSDSP_LLO;
tempRt = (uint64_t)rt & MIPSDSP_LLO;
--
1.7.9.5
- [Qemu-devel] [PATCH] target-mips: set carry bit correctly in DSPControl register,
Petar Jovanovic <=