Re: [Qemu-devel] [PATCH] target-mips: set carry bit correctly in DSPControl register

[Aurelien Jarno]

On Mon, May 13, 2013 at 05:14:35PM +0200, Petar Jovanovic wrote:
> From: Petar Jovanovic <address@hidden>
> 
> First we need to clear the bit and then we set the given value.
> Instruction ADDSC sets the bit and instruction ADDWC uses this bit.
> 
> Signed-off-by: Petar Jovanovic <address@hidden>
> ---
>  target-mips/dsp_helper.c |    7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index 9212789..e98bac8 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -53,9 +53,10 @@ static inline void set_DSPControl_overflow_flag(uint32_t 
> flag, int position,
>      env->active_tc.DSPControl |= (target_ulong)flag << position;
>  }
>  
> -static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
> +static inline void set_DSPControl_carryflag(bool flag, CPUMIPSState *env)
>  {
> -    env->active_tc.DSPControl |= (target_ulong)flag << 13;
> +    env->active_tc.DSPControl &= ~(1 << 13);
> +    env->active_tc.DSPControl |= flag << 13;
>  }
>  
>  static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
> @@ -1266,7 +1267,7 @@ SUBUH_QB(subuh_r, 1);
>  target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState 
> *env)
>  {
>      uint64_t temp, tempRs, tempRt;
> -    int32_t flag;
> +    bool flag;
>  
>      tempRs = (uint64_t)rs & MIPSDSP_LLO;
>      tempRt = (uint64_t)rt & MIPSDSP_LLO;

Thanks, applied.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net