Re: [Qemu-devel] [PATCH 13/19] Add VSX ISA2.06 Multiply Add Instructions

[Peter Maydell]

On 25 October 2013 17:25, Tom Musta <address@hidden> wrote:
> On 10/24/2013 3:38 PM, Richard Henderson wrote:
>> You want to be using tp##muladd instead of widening to 128 bits.
>
>
> I tried recoding xsmaddadp using float64_muladd.  The problem that I hit is
> the
> boundary case where the intermediate product and the summand are infinities
> of
> the opposite sign.  This is the case handled by the first "if" in the code
> snippet above.  PowerPC has a dedicated FPSCR bit for this type of condition
> (VXISI) as well as a general invalid operation bit (VX).  As far as I can
> tell,
> the softfloat code only has the equivalent of the VX bit.   Thus the
> implementation
> that I proposed is a more accurate representation of the Power ISA.

You could add the flag to the softfloat code -- this is what I did
for the somewhat ARM specific float_flag_output_denormal.

> The VSX code was modeled after the existing fmadd FPU instruction.  I
> suspect
> the author of that code wrote it this way for similar reasons.

I suspect it just predates the provision of fused multiply-add at
the softfloat level. It should ideally be rewritten to use the
softfloat functions.

Are you sure that doing the arithmetic with the softfloat 128 bit
float operations doesn't set the inexact flag anywhere it
shouldn't? (ie where the intermediate product is not exact in
128 bit format but the final result is exact in 64 or 32 bits).

-- PMM