Re: [Qemu-devel] outlined TLB lookup on x86

[Xin Tong]

On Thu, Nov 28, 2013 at 8:12 AM, Lluís Vilanova <address@hidden> wrote:

Xin Tong writes:

> Hi LIuis
> we can probably generate vector intrinsics using the tcg, e.g. add support to
> tcg to emit vector instructions directly in code cache

There was some discussion long ago about adding vector instructions to TCG, but
I don't remember what was the conclusion.

Also remember that using vector instructions will "emulate" a low-associativity
TLB; don't know how much better than a 1-way TLB will that be, though.

> why would a larger TLB make some operations slower, the TLB is a direct-mapped
> hash and lookup should be O(1) there. In the cputlb, the CPU_TLB_SIZE is always
> used to index into the TLB, i.e. (X & (CPU_TLB_SIZE -1)).

It would make TLB invalidations slower (e.g., see 'tlb_flush' in
"cputlb.c"). And right now QEMU performs full TLB invalidations more frequently
than the equivalent HW needs to, although I suppose that should be quantified
too.

you are right LIuis. QEMU does context switch quite more often that real hw, this is probably primarily due to the fact that QEMU is magnitude slower than real hw.  I am wondering where timer is emulated in QEMU system-x86_64. I imagine the guest OS must program the timers to do interrupt for context switches. 

Another question, what happens when a vcpu is stuck in an infinite loop ? QEMU must need an timer interrupt somewhere as well ?

Is my understanding correct ?

Xin  

Lluis

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