Re: [Qemu-devel] [RFC PATCH 04/21] target-arm: preserve RAO/WI bits of ARMv7 SCTLR

[Peter Crosthwaite]

On Wed, Dec 4, 2013 at 7:55 PM, Fedorov Sergey <address@hidden> wrote:
>
> On 12/03/2013 04:17 PM, Peter Crosthwaite wrote:
>>
>> On Tue, Dec 3, 2013 at 6:48 PM, Sergey Fedorov <address@hidden>
>> wrote:
>>>
>>> From: Svetlana Fedoseeva <address@hidden>
>>>
>>> Signed-off-by: Svetlana Fedoseeva <address@hidden>
>>> Signed-off-by: Sergey Fedorov <address@hidden>
>>> ---
>>>   target-arm/helper.c |    4 ++++
>>>   1 file changed, 4 insertions(+)
>>>
>>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>>> index 6642e53..d7922ad 100644
>>> --- a/target-arm/helper.c
>>> +++ b/target-arm/helper.c
>>> @@ -1507,6 +1507,10 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
>>>
>>>   static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
>>> uint64_t value)
>>>   {
>>> +    if (arm_feature(env, ARM_FEATURE_V7)) {
>>> +        value = value | 0x00c50078; /* This bits are RAO/WI */
>>
>> Magic number. "these bits ".
>
>
> Would be acceptable to substitute this magic number with "bitshifted
> constants combined with bitwise or", e.g. as in vmsa_ttbcr_raw_write()?
>

Yes I think so, that will make life easier for the big macro
conversion (one day) :)

Regards,
Peter

>
>>
>>> +    }
>>> +
>>>       env->cp15.c1_sys = value;
>>>       /* ??? Lots of these bits are not implemented.  */
>>>       /* This may enable/disable the MMU, so do a TLB flush.  */
>>> --
>>> 1.7.9.5
>>>
>>>
>>
>
> --
> Best regards,
> Sergey Fedorov, Junior Software Engineer,
> Samsung R&D Institute Rus.
> E-mail: address@hidden
>
>