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[Qemu-devel] [PULL 12/30] target-arm: Restrict check_ap() use of S and R
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/30] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier |
Date: |
Thu, 20 Feb 2014 11:17:16 +0000 |
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
the use of them in check_ap() so that we don't get incorrect results
for ARMv8 CPUs.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d9e94f2..13707a3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2767,6 +2767,9 @@ static inline int check_ap(CPUARMState *env, int ap, int
domain_prot,
switch (ap) {
case 0:
+ if (arm_feature(env, ARM_FEATURE_V7)) {
+ return 0;
+ }
if (access_type == 1)
return 0;
switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
--
1.8.5
- [Qemu-devel] [PULL 20/30] target-arm: Drop success/fail return from cpreg read and write functions, (continued)
- [Qemu-devel] [PULL 20/30] target-arm: Drop success/fail return from cpreg read and write functions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 21/30] target-arm: Remove unnecessary code now read/write fns can't fail, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 19/30] target-arm: Convert miscellaneous reginfo structs to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 08/30] softfloat: Support halving the result of muladd operation, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 04/30] target-arm: A64: Implement SIMD scalar indexed instructions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 02/30] target-arm: A64: Implement plain vector SIMD indexed element insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 14/30] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 17/30] target-arm: Convert performance monitor reginfo to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 15/30] target-arm: Stop underdecoding ARM946 PRBS registers, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 12/30] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier,
Peter Maydell <=
- [Qemu-devel] [PULL 18/30] target-arm: Convert generic timer reginfo to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 11/30] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 03/30] target-arm: A64: Implement long vector x indexed insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 13/30] target-arm: Remove unused ARMCPUState sr substruct, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 06/30] target-arm: A64: Implement SIMD FP compare and set insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 05/30] target-arm: A64: Implement scalar three different instructions, Peter Maydell, 2014/02/20
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2014/02/21