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[Qemu-devel] [PATCH v2 16/25] exec-all.h: Increase MAX_OP_PER_INSTR for
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 16/25] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder |
Date: |
Fri, 14 Mar 2014 18:38:05 +0000 |
The ARM A64 decoder's worst case number of TCG ops per instruction
is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures
store). Raise the MAX_OP_PER_INSTR define accordingly.
Signed-off-by: Peter Maydell <address@hidden>
---
include/exec/exec-all.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 502b7aa..f9ac332 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -44,7 +44,7 @@ struct TranslationBlock;
typedef struct TranslationBlock TranslationBlock;
/* XXX: make safe guess about sizes */
-#define MAX_OP_PER_INSTR 208
+#define MAX_OP_PER_INSTR 266
#if HOST_LONG_BITS == 32
#define MAX_OPC_PARAM_PER_ARG 2
--
1.9.0
- [Qemu-devel] [PATCH v2 21/25] target-arm: A64: Move handle_2misc_narrow function, (continued)
- [Qemu-devel] [PATCH v2 21/25] target-arm: A64: Move handle_2misc_narrow function, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 23/25] target-arm: A64: Implement FCVTXN, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 08/25] target-arm: A64: Implement SHLL, SHLL2, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement FRINT*, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 19/25] softfloat: export squash_input_denormal functions, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 05/25] target-arm: A64: Add remaining CLS/Z vector ops, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 06/25] target-arm: A64: Saturating and narrowing shift ops, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 17/25] target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 03/25] target-arm: A64: Add last AdvSIMD Integer to FP ops, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 18/25] target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 16/25] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 09/25] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 14/25] target-arm: A64: Implement SRI, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 12/25] target-arm: A64: List unsupported shift-imm opcodes, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 04/25] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 22/25] target-arm: A64: Implement scalar saturating narrow ops, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 02/25] target-arm: A64: Fix bug in add_sub_ext handling of rn, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 25/25] scripts/qemu-binfmt-conf.sh: Add AArch64 registration, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 01/25] target-arm: A64: Implement PMULL instruction, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 13/25] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 20/25] target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE, Peter Maydell, 2014/03/14