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Re: [Qemu-devel] [PATCH v3 01/26] tcg-aarch64: Properly detect SIGSEGV w


From: Richard Henderson
Subject: Re: [Qemu-devel] [PATCH v3 01/26] tcg-aarch64: Properly detect SIGSEGV writes
Date: Mon, 07 Apr 2014 09:33:16 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0

On 04/07/2014 12:58 AM, Claudio Fontana wrote:
>> +                || (insn & 0x3bc00000) == 0x28400000   /* C3.3.7 */
> 
> I think the Load (L) bit should be 0 here so
> 
> == 0x28000000

Oops.  Fixed.

> 
>> +                || (insn & 0x3be00c00) == 0x38000400   /* C3.3.8 */
> 
> With V=1, an opc of 0b10 is also a write, I think. It's the 128bit FP/SIMD 
> STR.

Exactly, that's why I'm masking it out, to ignore it.

 insn  =  size 1 1   1 v 0 0 ...
 mask  =   0 0 1 1   1 0 1 1 ...  = 0x3b...
 equal =   0 0 1 1   1 0 0 0 ...  = 0x38...


r~



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