Re: [Qemu-devel] [PATCH v3 01/26] tcg-aarch64: Properly detect SIGSEGV writes

[Richard Henderson]

On 04/14/2014 04:32 AM, Claudio Fontana wrote:
> the problem is not in the two nibbles you show, but in the third nibble:
> 31 30 29 28  27 26 25 24  23 22 21 20
>  size  1  1   1  v  0  0   opc   0  x
> 
> the third nibble in your mask is 'E' and the expected result is 0, which 
> forces opc to be 0 for writes.
> However, for 128bit SIMD STR, the opc is 2 (0b10).

Ah, I see what you mean.

Unfortunately, this means a simple mask won't work for this case;
it'll take two masks to decode that properly.


r~