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[Qemu-devel] [PATCH v3 11/12] target-i386: support "invariant tsc" flag
From: |
Eduardo Habkost |
Subject: |
[Qemu-devel] [PATCH v3 11/12] target-i386: support "invariant tsc" flag |
Date: |
Wed, 23 Apr 2014 17:29:39 -0300 |
From: Marcelo Tosatti <address@hidden>
Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation:
17.13.1 Invariant TSC The time stamp counter in newer processors may
support an enhancement, referred to as invariant TSC. Processor’s
support for invariant TSC is indicated by CPUID.80000007H:EDX[8].
The invariant TSC will run at a constant rate in all ACPI P-, C-.
and T-states. This is the architectural behavior moving forward. On
processors with invariant TSC support, the OS may use the TSC for wall
clock timer services (instead of ACPI or HPET timers). TSC reads are
much more efficient and do not incur the overhead associated with a ring
transition or access to a platform resource.
Signed-off-by: Marcelo Tosatti <address@hidden>
[ehabkost: redo feature filtering to use .tcg_features]
Signed-off-by: Eduardo Habkost <address@hidden>
---
target-i386/cpu.c | 26 ++++++++++++++++++++++++++
target-i386/cpu.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 198767f..bcd3a43 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -262,6 +262,17 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
+static const char *cpuid_apm_edx_feature_name[] = {
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ "invtsc", NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+ NULL, NULL, NULL, NULL,
+};
+
#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
@@ -319,6 +330,7 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
CPUID_7_0_EBX_RDSEED */
+#define TCG_APM_FEATURES 0
typedef struct FeatureWordInfo {
@@ -373,6 +385,12 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.cpuid_reg = R_EBX,
.tcg_features = TCG_7_0_EBX_FEATURES,
},
+ [FEAT_8000_0007_EDX] = {
+ .feat_names = cpuid_apm_edx_feature_name,
+ .cpuid_eax = 0x80000007,
+ .cpuid_reg = R_EDX,
+ .tcg_features = TCG_APM_FEATURES,
+ },
};
typedef struct X86RegisterInfo32 {
@@ -1731,6 +1749,7 @@ static void x86_cpu_parse_featurestr(CPUState *cs, char
*features,
env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
+ env->features[FEAT_8000_0007_EDX] |= plus_features[FEAT_8000_0007_EDX];
env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
@@ -1739,6 +1758,7 @@ static void x86_cpu_parse_featurestr(CPUState *cs, char
*features,
env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
+ env->features[FEAT_8000_0007_EDX] &= ~minus_features[FEAT_8000_0007_EDX];
env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
@@ -2345,6 +2365,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
(AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
(L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
break;
+ case 0x80000007:
+ *eax = 0;
+ *ebx = 0;
+ *ecx = 0;
+ *edx = env->features[FEAT_8000_0007_EDX];
+ break;
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
/* XXX: This value must match the one used in the MMU code. */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 2a22a7d..7ad980f 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -398,6 +398,7 @@ typedef enum FeatureWord {
FEAT_7_0_EBX, /* CPUID[EAX=7,ECX=0].EBX */
FEAT_8000_0001_EDX, /* CPUID[8000_0001].EDX */
FEAT_8000_0001_ECX, /* CPUID[8000_0001].ECX */
+ FEAT_8000_0007_EDX, /* CPUID[8000_0007].EDX */
FEAT_C000_0001_EDX, /* CPUID[C000_0001].EDX */
FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
FEAT_SVM, /* CPUID[8000_000A].EDX */
--
1.9.0
- [Qemu-devel] [PATCH v3 00/12] target-i386: Support check/enforce flags & -cpu host in TCG mode, too, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 04/12] target-i386: Isolate KVM-specific code on CPU feature filtering logic, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 01/12] target-i386: Simplify reporting of unavailable features, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 02/12] target-i386: Merge feature filtering/checking functions, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 10/12] target-i386: Support check/enforce flags in TCG mode, too, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 09/12] target-i386: Loop-based feature word filtering in TCG mode, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 11/12] target-i386: support "invariant tsc" flag,
Eduardo Habkost <=
- [Qemu-devel] [PATCH v3 08/12] target-i386: Define TCG_*_FEATURES earlier on cpu.c, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 12/12] target-i386: Support "-cpu host" in TCG mode, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 05/12] target-i386: Make TCG feature filtering more readable, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 03/12] target-i386: Pass FeatureWord argument to report_unavailable_features(), Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 06/12] target-i386: Filter FEAT_7_0_EBX TCG features too, Eduardo Habkost, 2014/04/23
- Re: [Qemu-devel] [PATCH v3 00/12] target-i386: Support check/enforce flags & -cpu host in TCG mode, too, Eduardo Habkost, 2014/04/23
- [Qemu-devel] [PATCH v3 07/12] target-i386: Filter KVM and 0xC0000001 features on TCG, Eduardo Habkost, 2014/04/23