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[Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to M
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode |
Date: |
Tue, 13 May 2014 18:16:07 +0200 |
SCR.{IRQ/FIQ} bits allows to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/cpu.h | 2 ++
target-arm/helper.c | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f6261c2..212cb64 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -673,6 +673,8 @@ static inline int arm_feature(CPUARMState *env, int feature)
}
#define SCR_NS (1U << 0)
+#define SCR_IRQ (1U << 1)
+#define SCR_FIQ (1U << 2)
/* Return true if the processor is in secure state */
static inline bool arm_is_secure(CPUARMState *env)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index deff3de..a5ba480 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3597,12 +3597,21 @@ void arm_cpu_do_interrupt(CPUState *cs)
/* Disable IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I;
offset = 4;
+ if (env->cp15.c1_scr & SCR_IRQ) {
+ /* IRQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ mask |= CPSR_F;
+ }
break;
case EXCP_FIQ:
new_mode = ARM_CPU_MODE_FIQ;
addr = 0x1c;
/* Disable FIQ, IRQ and imprecise data aborts. */
mask = CPSR_A | CPSR_I | CPSR_F;
+ if (env->cp15.c1_scr & SCR_FIQ) {
+ /* FIQ routed to monitor mode */
+ new_mode = ARM_CPU_MODE_MON;
+ }
offset = 4;
break;
case EXCP_SMC:
--
1.8.3.2
- [Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature, (continued)
- [Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature, Fabian Aggeler, 2014/05/13
- [Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition, Fabian Aggeler, 2014/05/13
- [Qemu-devel] [PATCH v2 07/23] target-arm: reject switching to monitor mode from non-secure state, Fabian Aggeler, 2014/05/13
- [Qemu-devel] [PATCH v2 08/23] target-arm: adjust arm_current_pl() for Security Extensions, Fabian Aggeler, 2014/05/13
- [Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode, Fabian Aggeler, 2014/05/13
- [Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR, Fabian Aggeler, 2014/05/13
- [Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode,
Fabian Aggeler <=
- [Qemu-devel] [PATCH v2 11/23] target-arm: add NSACR support, Fabian Aggeler, 2014/05/13
- [Qemu-devel] [PATCH v2 14/23] target-arm: add banked coprocessor register type and macros, Fabian Aggeler, 2014/05/13
- Re: [Qemu-devel] [PATCH v2 14/23] target-arm: add banked coprocessor register type and macros, Edgar E. Iglesias, 2014/05/22