Re: [Qemu-devel] [PATCH] target-arm: A64: Correct handling of UXN bit.

[Peter Maydell]

On 8 June 2014 14:53, Ian Campbell <address@hidden> wrote:
> In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
> and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we
> can just treat this bit as UXN whenever we are in v8 mode.
>
> Also correctly extract the upper attributes from the PTE entry, the v8 version
> tried to avoid extracting the CONTIG bit and ended up with the upper bits 
> being
> off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG
> bit.
>
> This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f"
> seen when modprobing modules under Linux.
>
> Signed-off-by: Ian Campbell <address@hidden>
> Cc: Peter Maydell <address@hidden>
> Cc: Claudio Fontana <address@hidden>
> Cc: Rob Herring <address@hidden>

Thanks, applied to target-arm.next.
To those interested in EL2/EL3 support: what's the
plan for telling the get_phys_addr() functions which
translation regime they should be operating in?

(since that is what indicates whether this bit is UXN or XN,
as well as having various other effects).

thanks
-- PMM