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Re: [Qemu-devel] [PATCH v5 02/10] target-arm: Add SCR_EL3
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v5 02/10] target-arm: Add SCR_EL3 |
Date: |
Tue, 19 Aug 2014 16:13:48 +0100 |
On 18 August 2014 10:40, Edgar E. Iglesias <address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
> ---
> target-arm/cpu.h | 17 ++++++++++++++++-
> target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++--
> 2 files changed, 49 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 8859b94..524eb90 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -172,7 +172,6 @@ typedef struct CPUARMState {
> uint64_t c1_sys; /* System control register. */
> uint64_t c1_coproc; /* Coprocessor access register. */
> uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
> - uint32_t c1_scr; /* secure config register. */
> uint64_t ttbr0_el1; /* MMU translation table base 0. */
> uint64_t ttbr1_el1; /* MMU translation table base 1. */
> uint64_t c2_control; /* MMU translation table base control. */
> @@ -185,6 +184,7 @@ typedef struct CPUARMState {
> uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
> uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
> uint64_t hcr_el2; /* Hypervisor configuration register */
> + uint32_t scr_el3; /* Secure configuration register. */
This is a uint32_t but you refer to it below with fieldoffset() in
an AArch64 reginfo -- it has to be a uint64_t for that.
> uint32_t ifsr_el2; /* Fault status registers. */
> uint64_t esr_el[4];
> uint32_t c6_region[8]; /* MPU base/size registers. */
> @@ -578,6 +578,21 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
> val, uint32_t mask)
> #define HCR_ID (1ULL << 33)
> #define HCR_MASK ((1ULL << 34) - 1)
>
> +#define SCR_NS (1U << 0)
> +#define SCR_IRQ (1U << 1)
> +#define SCR_FIQ (1U << 2)
> +#define SCR_EA (1U << 3)
> +#define SCR_SMD (1U << 7)
> +#define SCR_HCE (1U << 8)
> +#define SCR_SIF (1U << 9)
> +#define SCR_RW (1U << 10)
> +#define SCR_ST (1U << 11)
> +#define SCR_TWI (1U << 12)
> +#define SCR_TWE (1U << 13)
> +#define SCR_AARCH64_RES1_MASK (3U << 4)
> +#define SCR_AARCH32_MASK (0x3fff & ~(3U << 10))
> +#define SCR_AARCH64_MASK (0x3fff & ~(1U << 6))
I find these masks rather confusing to read...
> +
> /* Return the current FPSCR value. */
> uint32_t vfp_get_fpscr(CPUARMState *env);
> void vfp_set_fpscr(CPUARMState *env, uint32_t val);
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1021812..59144cd 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -684,6 +684,32 @@ static void vbar_write(CPUARMState *env, const
> ARMCPRegInfo *ri,
> raw_write(env, ri, value & ~0x1FULL);
> }
>
> +static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
> value)
> +{
> + uint32_t valid_mask = is_a64(env) ? SCR_AARCH64_MASK : SCR_AARCH32_MASK;
> + uint32_t res1_mask = is_a64(env) ? SCR_AARCH64_RES1_MASK : 0;
I don't think this is valid by the definition of RES0/RES1.
We're basically implementing SCR and SCR_EL3 as
aliased to each other. That means that bit 6 is RES0
for AArch64 but has a meaning in AArch32, which puts
it into the "RES0 only in some contexts" category.
That says "a direct write to the bit must update a storage
location associated with the bit" -- we can't mask it out
here.
thanks
-- PMM
- [Qemu-devel] [PATCH v5 00/10] target-arm: Parts of the AArch64 EL2/3 exception model, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 01/10] target-arm: Add HCR_EL2, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 02/10] target-arm: Add SCR_EL3, Edgar E. Iglesias, 2014/08/18
- Re: [Qemu-devel] [PATCH v5 02/10] target-arm: Add SCR_EL3,
Peter Maydell <=
- [Qemu-devel] [PATCH v5 03/10] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 04/10] target-arm: Break out exception masking to a separate func, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 05/10] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 06/10] target-arm: A64: Correct updates to FAR and ESR on exceptions, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 07/10] target-arm: A64: Emulate the HVC insn, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 08/10] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 09/10] target-arm: Add IRQ and FIQ routing to EL2 and 3, Edgar E. Iglesias, 2014/08/18
- [Qemu-devel] [PATCH v5 10/10] target-arm: Add support for VIRQ and VFIQ, Edgar E. Iglesias, 2014/08/18