[Qemu-devel] [PULL 00/34] target-mips queue

[Leon Alrae]

Hi,

This pull request contains remaining MIPS patches which are on the mailing
list for a long time. I think it is worth putting them into stable 2.2 version
as these two significant MIPS features are already tested, moreover the MSA
feature is quite isolated piece of work and most of those 6000 lines just
implement new instructions.
Sorry for sending this pull request just before hard-freeze.

Thanks,
Leon

Cc: Peter Maydell <address@hidden>
Cc: Aurelien Jarno <address@hidden>

The following changes since commit 0a2923f8488498000eec54871456aa64a4391da4:

  tcg/mips: fix store softmmu slow path (2014-11-02 13:30:00 +0100)

are available in the git repository at:

  git://github.com/lalrae/qemu.git tags/mips-20141103

for you to fetch changes up to 55a2201e79d063766509ed2f2f2e8837b9e1facf:

  target-mips: add MSA support to mips32r5-generic (2014-11-03 11:48:35 +0000)

----------------------------------------------------------------
MIPS patches 2014-11-03

Changes:
* second part (privileged) of MIPS64R6 support
* MIPS SIMD Architecture support

----------------------------------------------------------------
Leon Alrae (15):
      target-mips: add KScratch registers
      softmmu: provide softmmu access type enum
      target-mips: distinguish between data load and instruction fetch
      target-mips: add RI and XI fields to TLB entry
      target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}
      target-mips: add new Read-Inhibit and Execute-Inhibit exceptions
      target-mips: add TLBINV support
      target-mips: add BadInstr and BadInstrP support
      target-mips: update cpu_save/cpu_load to support new registers
      target-mips: add Config5.SBRI
      target-mips: implement forbidden slot
      target-mips: CP0_Status.CU0 no longer allows the user to access CP0
      target-mips: add restrictions for possible values in registers
      target-mips: correctly handle access to unimplemented CP0 register
      target-mips: enable features in MIPS64R6-generic CPU

Yongbok Kim (19):
      target-mips: add MSA defines and data structure
      target-mips: add MSA exceptions
      target-mips: remove duplicated mips/ieee mapping function
      target-mips: stop translation after ctc1
      target-mips: add MSA opcode enum
      target-mips: add msa_reset(), global msa register
      target-mips: add msa_helper.c
      target-mips: add MSA branch instructions
      target-mips: add MSA I8 format instructions
      target-mips: add MSA I5 format instruction
      target-mips: add MSA BIT format instructions
      target-mips: add MSA 3R format instructions
      target-mips: add MSA ELM format instructions
      target-mips: add MSA 3RF format instructions
      target-mips: add MSA VEC/2R format instructions
      target-mips: add MSA 2RF format instructions
      target-mips: add MSA MI10 format instructions
      disas/mips.c: disassemble MSA instructions
      target-mips: add MSA support to mips32r5-generic

 disas/mips.c                 |  718 ++++++++-
 include/exec/cpu-common.h    |    6 +
 softmmu_template.h           |   26 +-
 target-mips/Makefile.objs    |    2 +-
 target-mips/cpu.h            |  107 +-
 target-mips/gdbstub.c        |    7 -
 target-mips/helper.c         |  114 +-
 target-mips/helper.h         |  191 +++
 target-mips/machine.c        |   26 +-
 target-mips/mips-defs.h      |    1 +
 target-mips/msa_helper.c     | 3436 ++++++++++++++++++++++++++++++++++++++++++
 target-mips/op_helper.c      |  272 +++-
 target-mips/translate.c      | 2386 ++++++++++++++++++++++++-----
 target-mips/translate_init.c |   53 +-
 14 files changed, 6874 insertions(+), 471 deletions(-)
 create mode 100644 target-mips/msa_helper.c