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[Qemu-devel] [PULL 10/34] target-mips: add Config5.SBRI
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 10/34] target-mips: add Config5.SBRI |
Date: |
Mon, 3 Nov 2014 16:11:24 +0000 |
SDBBP instruction Reserved Instruction control. The purpose of this field is
to restrict availability of SDBBP to kernel mode operation.
If the bit is set then SDBBP instruction can only be executed in kernel mode.
User execution of SDBBP will cause a Reserved Instruction exception.
Additionally add missing Config4 and Config5 cases for dm{f,t}c0.
Signed-off-by: Leon Alrae <address@hidden>
Reviewed-by: Yongbok Kim <address@hidden>
---
target-mips/cpu.h | 11 +++++++++--
target-mips/translate.c | 24 +++++++++++++++++++++++-
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index c66a725..ce9a7a2 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -410,6 +410,7 @@ struct CPUMIPSState {
#define CP0C5_CV 29
#define CP0C5_EVA 28
#define CP0C5_MSAEn 27
+#define CP0C5_SBRI 6
#define CP0C5_UFR 2
#define CP0C5_NFExists 0
int32_t CP0_Config6;
@@ -461,7 +462,7 @@ struct CPUMIPSState {
#define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
uint32_t hflags; /* CPU State */
/* TMASK defines different execution modes */
-#define MIPS_HFLAG_TMASK 0x1807FF
+#define MIPS_HFLAG_TMASK 0x5807FF
#define MIPS_HFLAG_MODE 0x00007 /* execution modes */
/* The KSU flags must be the lowest bits in hflags. The flag order
must be the same as defined for CP0 Status. This allows to use
@@ -505,6 +506,7 @@ struct CPUMIPSState {
#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
/* Extra flag about HWREna register. */
#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
+#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
target_ulong btarget; /* Jump / branch target */
target_ulong bcond; /* Branch condition (if needed) */
@@ -760,7 +762,8 @@ static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
- MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
+ MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
+ MIPS_HFLAG_SBRI);
if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) {
@@ -796,6 +799,10 @@ static inline void compute_hflags(CPUMIPSState *env)
if (env->CP0_Status & (1 << CP0St_FR)) {
env->hflags |= MIPS_HFLAG_F64;
}
+ if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
+ (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
+ env->hflags |= MIPS_HFLAG_SBRI;
+ }
if (env->insn_flags & ASE_DSPR2) {
/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
so enable to access DSPR2 resources. */
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 3e6e990..c7a8bbc 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -6225,6 +6225,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
rn = "Config3";
break;
+ case 4:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
+ rn = "Config4";
+ break;
+ case 5:
+ gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
+ rn = "Config5";
+ break;
/* 6,7 are implementation dependent */
case 6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
@@ -6843,6 +6851,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
/* ignored */
rn = "Config3";
break;
+ case 4:
+ /* currently ignored */
+ rn = "Config4";
+ break;
+ case 5:
+ gen_helper_mtc0_config5(cpu_env, arg);
+ rn = "Config5";
+ /* Stop translation as we may have switched the execution mode */
+ ctx->bstate = BS_STOP;
+ break;
/* 6,7 are implementation dependent */
default:
rn = "Invalid config selector";
@@ -15801,7 +15819,11 @@ static void decode_opc_special_r6(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case R6_OPC_SDBBP:
- generate_exception(ctx, EXCP_DBp);
+ if (ctx->hflags & MIPS_HFLAG_SBRI) {
+ generate_exception(ctx, EXCP_RI);
+ } else {
+ generate_exception(ctx, EXCP_DBp);
+ }
break;
#if defined(TARGET_MIPS64)
case OPC_DLSA:
--
2.1.0
- [Qemu-devel] [PULL 00/34] target-mips queue, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 01/34] target-mips: add KScratch registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 03/34] target-mips: distinguish between data load and instruction fetch, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 02/34] softmmu: provide softmmu access type enum, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 06/34] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 04/34] target-mips: add RI and XI fields to TLB entry, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 05/34] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1}, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 12/34] target-mips: CP0_Status.CU0 no longer allows the user to access CP0, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 08/34] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 07/34] target-mips: add TLBINV support, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 10/34] target-mips: add Config5.SBRI,
Leon Alrae <=
- [Qemu-devel] [PULL 11/34] target-mips: implement forbidden slot, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 13/34] target-mips: add restrictions for possible values in registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 09/34] target-mips: update cpu_save/cpu_load to support new registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 15/34] target-mips: enable features in MIPS64R6-generic CPU, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 16/34] target-mips: add MSA defines and data structure, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 17/34] target-mips: add MSA exceptions, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 19/34] target-mips: stop translation after ctc1, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 18/34] target-mips: remove duplicated mips/ieee mapping function, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 22/34] target-mips: add msa_helper.c, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 21/34] target-mips: add msa_reset(), global msa register, Leon Alrae, 2014/11/03