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[Qemu-devel] [PULL 19/34] target-mips: stop translation after ctc1
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 19/34] target-mips: stop translation after ctc1 |
Date: |
Mon, 3 Nov 2014 16:11:33 +0000 |
From: Yongbok Kim <address@hidden>
stop translation as ctc1 instruction can change hflags
Reviewed-by: James Hogan <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 9a8f5c9..b388ba5 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7490,12 +7490,15 @@ static void gen_mttr(CPUMIPSState *env, DisasContext
*ctx, int rd, int rt,
break;
case 3:
/* XXX: For now we support only a single FPU context. */
+ save_cpu_state(ctx, 1);
{
TCGv_i32 fs_tmp = tcg_const_i32(rd);
gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
tcg_temp_free_i32(fs_tmp);
}
+ /* Stop translation as we may have changed hflags */
+ ctx->bstate = BS_STOP;
break;
/* COP2: Not implemented. */
case 4:
@@ -8089,12 +8092,15 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc,
int rt, int fs)
break;
case OPC_CTC1:
gen_load_gpr(t0, rt);
+ save_cpu_state(ctx, 1);
{
TCGv_i32 fs_tmp = tcg_const_i32(fs);
gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
tcg_temp_free_i32(fs_tmp);
}
+ /* Stop translation as we may have changed hflags */
+ ctx->bstate = BS_STOP;
opn = "ctc1";
break;
#if defined(TARGET_MIPS64)
--
2.1.0
- [Qemu-devel] [PULL 12/34] target-mips: CP0_Status.CU0 no longer allows the user to access CP0, (continued)
- [Qemu-devel] [PULL 12/34] target-mips: CP0_Status.CU0 no longer allows the user to access CP0, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 08/34] target-mips: add BadInstr and BadInstrP support, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 07/34] target-mips: add TLBINV support, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 10/34] target-mips: add Config5.SBRI, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 11/34] target-mips: implement forbidden slot, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 13/34] target-mips: add restrictions for possible values in registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 09/34] target-mips: update cpu_save/cpu_load to support new registers, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 15/34] target-mips: enable features in MIPS64R6-generic CPU, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 16/34] target-mips: add MSA defines and data structure, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 17/34] target-mips: add MSA exceptions, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 19/34] target-mips: stop translation after ctc1,
Leon Alrae <=
- [Qemu-devel] [PULL 18/34] target-mips: remove duplicated mips/ieee mapping function, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 22/34] target-mips: add msa_helper.c, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 21/34] target-mips: add msa_reset(), global msa register, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 23/34] target-mips: add MSA branch instructions, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 20/34] target-mips: add MSA opcode enum, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 14/34] target-mips: correctly handle access to unimplemented CP0 register, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 25/34] target-mips: add MSA I5 format instruction, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 24/34] target-mips: add MSA I8 format instructions, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 26/34] target-mips: add MSA BIT format instructions, Leon Alrae, 2014/11/03
- [Qemu-devel] [PULL 27/34] target-mips: add MSA 3R format instructions, Leon Alrae, 2014/11/03