[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 10/33] target-arm: move AArch32 SCR into security reg
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/33] target-arm: move AArch32 SCR into security reglist |
Date: |
Thu, 11 Dec 2014 12:19:32 +0000 |
From: Fabian Aggeler <address@hidden>
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving AArch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 96284f1..d3180dd 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -898,9 +898,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.access = PL1_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
.resetvalue = 0 },
- { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.scr_el3),
- .resetvalue = 0, .writefn = scr_write },
{ .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
.access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
@@ -2335,11 +2332,18 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.access = PL3_RW, .writefn = vbar_write,
.fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
.resetvalue = 0 },
+ REGINFO_SENTINEL
+};
+
+static const ARMCPRegInfo el3_cp_reginfo[] = {
{ .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
- .writefn = scr_write },
+ .resetvalue = 0, .writefn = scr_write },
+ { .name = "SCR", .type = ARM_CP_NO_MIGRATE,
+ .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
+ .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.scr_el3),
+ .resetfn = arm_cp_reset_ignore, .writefn = scr_write },
REGINFO_SENTINEL
};
@@ -2960,7 +2964,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
if (arm_feature(env, ARM_FEATURE_EL3)) {
- define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
+ if (arm_feature(env, ARM_FEATURE_V8)) {
+ define_arm_cp_regs(cpu, v8_el3_cp_reginfo);
+ }
+ define_arm_cp_regs(cpu, el3_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_MPU)) {
/* These are the MPU registers prior to PMSAv6. Any new
--
1.9.1
- [Qemu-devel] [PULL 17/33] target-arm: make CSSELR banked, (continued)
- [Qemu-devel] [PULL 17/33] target-arm: make CSSELR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 18/33] target-arm: make TTBR0/1 banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 19/33] target-arm: make TTBCR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 16/33] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 22/33] target-arm: make DFSR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 14/33] target-arm: add MVBAR support, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 12/33] target-arm: add NSACR register, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 25/33] target-arm: make VBAR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 15/33] target-arm: add SCTLR_EL3 and make SCTLR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 11/33] target-arm: implement IRQ/FIQ routing to Monitor mode, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 10/33] target-arm: move AArch32 SCR into security reglist,
Peter Maydell <=
- [Qemu-devel] [PULL 09/33] target-arm: insert AArch32 cpregs twice into hashtable, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 07/33] target-arm: add CPREG secure state support, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 06/33] target-arm: add non-secure Translation Block flag, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 05/33] target-arm: add banked register accessors, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 02/33] Add the "-semihosting-config" option., Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 20/33] target-arm: make DACR banked, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 08/33] target-arm: add secure state bit to CPREG hash, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 03/33] target-arm: extend async excp masking, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 13/33] target-arm: add SDER definition, Peter Maydell, 2014/12/11
- [Qemu-devel] [PULL 01/33] Pass semihosting exit code back to system., Peter Maydell, 2014/12/11