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[Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 |
Date: |
Fri, 12 Dec 2014 17:31:37 +0000 |
Those makros are exclusively used for 32 bit arithmetics and won't work for 16
bit with two halfwords.
So lets get rid of the len parameter and make them always use 32 bit.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/op_helper.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 4da76ff..3843348 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -56,9 +56,9 @@ uint32_t helper_circ_update(uint32_t reg, uint32_t off)
return reg - index + new_index;
}
-#define SSOV(env, ret, arg, len) do { \
- int64_t max_pos = INT##len ##_MAX; \
- int64_t max_neg = INT##len ##_MIN; \
+#define SSOV32(env, ret, arg) do { \
+ int64_t max_pos = INT32_MAX; \
+ int64_t max_neg = INT32_MIN; \
if (arg > max_pos) { \
env->PSW_USB_V = (1 << 31); \
env->PSW_USB_SV = (1 << 31); \
@@ -77,8 +77,8 @@ uint32_t helper_circ_update(uint32_t reg, uint32_t off)
env->PSW_USB_SAV |= env->PSW_USB_AV; \
} while (0)
-#define SUOV(env, ret, arg, len) do { \
- int64_t max_pos = UINT##len ##_MAX; \
+#define SUOV32(env, ret, arg) do { \
+ int64_t max_pos = UINT32_MAX; \
if (arg > max_pos) { \
env->PSW_USB_V = (1 << 31); \
env->PSW_USB_SV = (1 << 31); \
@@ -105,7 +105,7 @@ target_ulong helper_add_ssov(CPUTriCoreState *env,
target_ulong r1,
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
int64_t result = t1 + t2;
- SSOV(env, ret, result, 32);
+ SSOV32(env, ret, result);
return ret;
}
@@ -116,7 +116,7 @@ target_ulong helper_add_suov(CPUTriCoreState *env,
target_ulong r1,
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
int64_t result = t1 + t2;
- SUOV(env, ret, result, 32);
+ SUOV32(env, ret, result);
return ret;
}
@@ -127,7 +127,7 @@ target_ulong helper_sub_ssov(CPUTriCoreState *env,
target_ulong r1,
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
int64_t result = t1 - t2;
- SSOV(env, ret, result, 32);
+ SSOV32(env, ret, result);
return ret;
}
@@ -138,7 +138,7 @@ target_ulong helper_sub_suov(CPUTriCoreState *env,
target_ulong r1,
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
int64_t result = t1 - t2;
- SUOV(env, ret, result, 32);
+ SUOV32(env, ret, result);
return ret;
}
@@ -149,7 +149,7 @@ target_ulong helper_mul_ssov(CPUTriCoreState *env,
target_ulong r1,
int64_t t1 = sextract64(r1, 0, 32);
int64_t t2 = sextract64(r2, 0, 32);
int64_t result = t1 * t2;
- SSOV(env, ret, result, 32);
+ SSOV32(env, ret, result);
return ret;
}
@@ -160,7 +160,7 @@ target_ulong helper_mul_suov(CPUTriCoreState *env,
target_ulong r1,
int64_t t1 = extract64(r1, 0, 32);
int64_t t2 = extract64(r2, 0, 32);
int64_t result = t1 * t2;
- SUOV(env, ret, result, 32);
+ SUOV32(env, ret, result);
return ret;
}
@@ -178,7 +178,7 @@ target_ulong helper_sha_ssov(CPUTriCoreState *env,
target_ulong r1,
} else {
result = t1 >> -t2;
}
- SSOV(env, ret, result, 32);
+ SSOV32(env, ret, result);
return ret;
}
@@ -195,7 +195,7 @@ target_ulong helper_absdif_ssov(CPUTriCoreState *env,
target_ulong r1,
} else {
result = t2 - t1;
}
- SSOV(env, ret, result, 32);
+ SSOV32(env, ret, result);
return ret;
}
@@ -209,7 +209,7 @@ target_ulong helper_madd32_ssov(CPUTriCoreState *env,
target_ulong r1,
int64_t result;
result = t2 + (t1 * t3);
- SSOV(env, ret, result, 32);
+ SSOV32(env, ret, result);
return ret;
}
@@ -223,7 +223,7 @@ target_ulong helper_madd32_suov(CPUTriCoreState *env,
target_ulong r1,
int64_t result;
result = t2 + (t1 * t3);
- SUOV(env, ret, result, 32);
+ SUOV32(env, ret, result);
return ret;
}
@@ -293,7 +293,7 @@ target_ulong helper_msub32_ssov(CPUTriCoreState *env,
target_ulong r1,
int64_t result;
result = t2 - (t1 * t3);
- SSOV(env, ret, result, 32);
+ SSOV32(env, ret, result);
return ret;
}
@@ -307,7 +307,7 @@ target_ulong helper_msub32_suov(CPUTriCoreState *env,
target_ulong r1,
int64_t result;
result = t2 - (t1 * t3);
- SUOV(env, ret, result, 32);
+ SUOV32(env, ret, result);
return ret;
}
--
2.1.3
- Re: [Qemu-devel] [PATCH 4/8] target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode, (continued)
- [Qemu-devel] [PATCH 3/8] target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 5/8] target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 7/8] target-tricore: Fix MFCR/MTCR insn and B format offset., Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 8/8] target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 1/8] target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32,
Bastian Koppelmann <=
- [Qemu-devel] [PATCH 6/8] target-tricore: Add missing 1.6 insn of BOL opcode format, Bastian Koppelmann, 2014/12/12
- [Qemu-devel] [PATCH 2/8] target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode, Bastian Koppelmann, 2014/12/12