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[Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments |
Date: |
Thu, 19 Feb 2015 13:14:18 -0800 |
While doing the mechanics of a previous patch set converting
translators to use to TCGLabel pointers, I was reminded of
several outstanding OPTME comments in the aarch64 translator.
I had started with the csel change, which at first failed and
took quite some time to debug. See the comment for patch 1.
Since this depends on the outstanding TCGLabel patch set, the
full tree is available at
git://github.com/rth7680/qemu.git arm-movcond
r~
Richard Henderson (11):
target-arm: Introduce DisasCompare
target-arm: Extend NZCF to 64 bits
target-arm: Handle always condition codes within arm_test_cc
target-arm: Recognize SXTB, SXTH, SXTW, ASR
target-arm: Recognize UXTB, UXTH, LSR, LSL
target-arm: Eliminate unnecessary zero-extend in disas_bitfield
target-arm: Recognize ROR
target-arm: Use setcond and movcond for csel
target-arm: Implement ccmp branchless
target-arm: Implement fccmp branchless
target-arm: Implement fcsel with movcond
target-arm/cpu.h | 21 +-
target-arm/helper.c | 18 +-
target-arm/translate-a64.c | 688 ++++++++++++++++++++++++++-------------------
target-arm/translate.c | 151 ++++++----
target-arm/translate.h | 2 -
5 files changed, 524 insertions(+), 356 deletions(-)
--
2.1.0
- [Qemu-devel] [PATCH 00/11] target-aarch64 fix and improvments,
Richard Henderson <=
- [Qemu-devel] [PATCH 03/11] target-arm: Handle always condition codes within arm_test_cc, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 04/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 01/11] target-arm: Introduce DisasCompare, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 05/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 02/11] target-arm: Extend NZCF to 64 bits, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 08/11] target-arm: Use setcond and movcond for csel, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 09/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 06/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 07/11] target-arm: Recognize ROR, Richard Henderson, 2015/02/19
- [Qemu-devel] [PATCH 10/11] target-arm: Implement fccmp branchless, Richard Henderson, 2015/02/19