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[Qemu-devel] [PULL 3/5] target-tricore: fix BO_OFF10_SEXT calculating th
From: |
Bastian Koppelmann |
Subject: |
[Qemu-devel] [PULL 3/5] target-tricore: fix BO_OFF10_SEXT calculating the wrong offset |
Date: |
Mon, 11 May 2015 14:30:14 +0200 |
The lower part of the combined offset was sign extended and could lead to
wrong results.
Signed-off-by: Bastian Koppelmann <address@hidden>
---
target-tricore/tricore-opcodes.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h
index d3a9bc1..2291f75 100644
--- a/target-tricore/tricore-opcodes.h
+++ b/target-tricore/tricore-opcodes.h
@@ -107,7 +107,7 @@
/* BO Format */
#define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT(op, 28, 31) << 6))
-#define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
+#define MASK_OP_BO_OFF10_SEXT(op) (MASK_BITS_SHIFT(op, 16, 21) + \
(MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
#define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
#define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
--
2.4.0
- [Qemu-devel] [PULL 0/5] tricore-patches, Bastian Koppelmann, 2015/05/11
- [Qemu-devel] [PULL 2/5] target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory access insted of 4, Bastian Koppelmann, 2015/05/11
- [Qemu-devel] [PULL 3/5] target-tricore: fix BO_OFF10_SEXT calculating the wrong offset,
Bastian Koppelmann <=
- [Qemu-devel] [PULL 1/5] target-tricore: Fix LOOP using wrong register for compare, Bastian Koppelmann, 2015/05/11
- [Qemu-devel] [PULL 4/5] target-tricore: fix rslcx restoring the upper context instead of the lower, Bastian Koppelmann, 2015/05/11
- [Qemu-devel] [PULL 5/5] target-tricore: fix rfe not restoring the PC, Bastian Koppelmann, 2015/05/11
- Re: [Qemu-devel] [PULL 0/5] tricore-patches, Peter Maydell, 2015/05/11