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Re: [Qemu-devel] [PATCH target-arm v1 5/9] arm: helper: rename get_phys_
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH target-arm v1 5/9] arm: helper: rename get_phys_addr_mpu |
Date: |
Mon, 1 Jun 2015 19:56:50 +0100 |
On 1 June 2015 at 19:04, Peter Crosthwaite <address@hidden> wrote:
> This get_phys_addr is really for pmsav5. Rename it accordingly.
>
> Signed-off-by: Peter Crosthwaite <address@hidden>
> ---
> target-arm/helper.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index f11efea..63859a4 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -5720,9 +5720,9 @@ do_fault:
> return (1 << 9) | (fault_type << 2) | level;
> }
>
> -static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
> - int access_type, ARMMMUIdx mmu_idx,
> - hwaddr *phys_ptr, int *prot)
> +static int get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
> + int access_type, ARMMMUIdx mmu_idx,
> + hwaddr *phys_ptr, int *prot)
> {
> int n;
> uint32_t mask;
> @@ -5857,8 +5857,8 @@ static inline int get_phys_addr(CPUARMState *env,
> target_ulong address,
>
> if (arm_feature(env, ARM_FEATURE_MPU)) {
> *page_size = TARGET_PAGE_SIZE;
> - return get_phys_addr_mpu(env, address, access_type, mmu_idx,
> phys_ptr,
> - prot);
> + return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
> + phys_ptr, prot);
> }
>
> if (regime_using_lpae_format(env, mmu_idx)) {
> --
> 2.4.2.3.g2ffcb72
>
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-devel] [PATCH target-arm v1 3/9] target-arm/helper.c: define MPUIR register, (continued)
[Qemu-devel] [PATCH target-arm v1 4/9] target-arm: Add registers for PMSAv7, Peter Crosthwaite, 2015/06/01
[Qemu-devel] [PATCH target-arm v1 5/9] arm: helper: rename get_phys_addr_mpu, Peter Crosthwaite, 2015/06/01
- Re: [Qemu-devel] [PATCH target-arm v1 5/9] arm: helper: rename get_phys_addr_mpu,
Peter Maydell <=
[Qemu-devel] [PATCH target-arm v1 6/9] target-arm: Implement PMSAv7 MPU, Peter Crosthwaite, 2015/06/01
[Qemu-devel] [PATCH target-arm v1 7/9] arm: r5: Implement dummy ATCM, BTCM and D-cache invalidate, Peter Crosthwaite, 2015/06/01
[Qemu-devel] [PATCH target-arm v1 8/9] arm: xlnx-zynqmp: Preface CPU variables with "A", Peter Crosthwaite, 2015/06/01