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[Qemu-devel] [PATCH for-2.4 1/2] target-mips: fix page fault address for
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH for-2.4 1/2] target-mips: fix page fault address for LWL/LWR/LDL/LDR |
Date: |
Tue, 14 Jul 2015 17:45:16 +0200 |
When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU
currently reports the aligned address in CP0 BadVAddr, while the Windows
NT kernel expects the unaligned address.
This patch adds a byte access with the unaligned address at the
beginning of the LWL/LWR/LDL/LDR instructions to possibly trigger a page
fault and fill the QEMU TLB.
Cc: Leon Alrae <address@hidden>
Reported-by: Hervé Poussineau <address@hidden>
Tested-by: Hervé Poussineau <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-mips/translate.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7302857..0ac3bd8 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2142,6 +2142,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break;
case OPC_LDL:
t1 = tcg_temp_new();
+ /* Do a byte access to possibly trigger a page
+ fault with the unaligned address. */
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 7);
#ifndef TARGET_WORDS_BIGENDIAN
tcg_gen_xori_tl(t1, t1, 7);
@@ -2163,6 +2166,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break;
case OPC_LDR:
t1 = tcg_temp_new();
+ /* Do a byte access to possibly trigger a page
+ fault with the unaligned address. */
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 7);
#ifdef TARGET_WORDS_BIGENDIAN
tcg_gen_xori_tl(t1, t1, 7);
@@ -2229,6 +2235,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break;
case OPC_LWL:
t1 = tcg_temp_new();
+ /* Do a byte access to possibly trigger a page
+ fault with the unaligned address. */
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 3);
#ifndef TARGET_WORDS_BIGENDIAN
tcg_gen_xori_tl(t1, t1, 3);
@@ -2251,6 +2260,9 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
break;
case OPC_LWR:
t1 = tcg_temp_new();
+ /* Do a byte access to possibly trigger a page
+ fault with the unaligned address. */
+ tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_UB);
tcg_gen_andi_tl(t1, t0, 3);
#ifdef TARGET_WORDS_BIGENDIAN
tcg_gen_xori_tl(t1, t1, 3);
--
2.1.4