Re: [Qemu-devel] [PATCH 1/6] ARM: add Cortex-M3/M4 exception configuration and status registers

[Peter Maydell]

On 7 July 2015 at 19:25, Alex Zuepke <address@hidden> wrote:
>
> Signed-off-by: Alex Zuepke <address@hidden>
> ---
>  target-arm/cpu.h     |   51 
> ++++++++++++++++++++++++++++++++++++++++++++++++++
>  target-arm/machine.c |    6 ++++++
>  2 files changed, 57 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 80297b3..1089f63 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -387,6 +387,12 @@ typedef struct CPUARMState {
>          uint32_t control;
>          int current_sp;
>          int exception;
> +        uint32_t ccr;
> +        uint32_t cfsr;
> +        uint32_t hfsr;
> +        uint32_t dfsr;
> +        uint32_t mmfar;
> +        uint32_t bfar;
>      } v7m;
>
>      /* Information associated with an exception about to be taken:
> @@ -852,6 +858,51 @@ enum arm_cpu_mode {
>  #define ARM_IWMMXT_wCGR2       10
>  #define ARM_IWMMXT_wCGR3       11
>
> +/* V7M CCSR bits */

Typo, should read "CCR".

> +#define CCR_STKALIGN        0x00000200
> +#define CCR_BFHFNMIGN       0x00000100
> +#define CCR_DIV_0_TRP       0x00000010
> +#define CCR_UNALIGN_TRP     0x00000008
> +#define CCR_USERSETMPEND    0x00000002
> +#define CCR_NONBASETHRDENA  0x00000001
> +
> +/* V7M CFSR bits for UFSR */
> +#define CFSR_DIVBYZERO      0x02000000
> +#define CFSR_UNALIGNED      0x01000000
> +#define CFSR_NOCP           0x00080000
> +#define CFSR_INVPC          0x00040000
> +#define CFSR_INVSTATE       0x00020000
> +#define CFSR_UNDEFINSTR     0x00010000
> +
> +/* V7M CFSR bits for BFSR */
> +#define CFSR_BFARVALID      0x00008000
> +#define CFSR_LSPERR         0x00002000
> +#define CFSR_STKERR         0x00001000
> +#define CFSR_UNSTKERR       0x00000800
> +#define CFSR_IMPRECISERR    0x00000400
> +#define CFSR_PRECISERR      0x00000200
> +#define CFSR_IBUSERR        0x00000100
> +
> +/* V7M CFSR bits for MMFSR */
> +#define CFSR_MMARVALID      0x00000080
> +#define CFSR_MLSPERR        0x00000020
> +#define CFSR_MSTKERR        0x00000010
> +#define CFSR_MUNSTKERR      0x00000008
> +#define CFSR_DACCVIOL       0x00000002
> +#define CFSR_IACCVIOL       0x00000001
> +
> +/* V7M HFSR bits */
> +#define HFSR_DEBUG_VT       0x80000000

This bit is DEBUGEVT, not DEBUG_VT.

> +#define HFSR_FORCED         0x40000000
> +#define HFSR_VECTTBL        0x00000002
> +
> +/* V7M DFSR bits */
> +#define DFSR_EXTERNAL       0x00000010
> +#define DFSR_VCATCH         0x00000008
> +#define DFSR_DWTTRAP        0x00000004
> +#define DFSR_BKPT           0x00000002
> +#define DFSR_HALTED         0x00000001
> +
>  /* If adding a feature bit which corresponds to a Linux ELF
>   * HWCAP bit, remember to update the feature-bit-to-hwcap
>   * mapping in linux-user/elfload.c:get_elf_hwcap().
> diff --git a/target-arm/machine.c b/target-arm/machine.c
> index 9eb51df..11dcf29 100644
> --- a/target-arm/machine.c
> +++ b/target-arm/machine.c
> @@ -101,6 +101,12 @@ static const VMStateDescription vmstate_m = {
>          VMSTATE_UINT32(env.v7m.control, ARMCPU),
>          VMSTATE_INT32(env.v7m.current_sp, ARMCPU),
>          VMSTATE_INT32(env.v7m.exception, ARMCPU),
> +        VMSTATE_UINT32(env.v7m.ccr, ARMCPU),
> +        VMSTATE_UINT32(env.v7m.cfsr, ARMCPU),
> +        VMSTATE_UINT32(env.v7m.hfsr, ARMCPU),
> +        VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),
> +        VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),
> +        VMSTATE_UINT32(env.v7m.bfar, ARMCPU),
>          VMSTATE_END_OF_LIST()

If you're adding entries to this VMStateDescription you
also need to increment its version_id and minimum_version_id
fields.

thanks
-- PMM