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[Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs |
Date: |
Tue, 25 Aug 2015 16:00:16 +0100 |
Implement the AArch64 TLBI operations which take an intermediate
physical address and invalidate stage 2 translations.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 00ecda9..7df1f06 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2709,6 +2709,45 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env,
const ARMCPRegInfo *ri,
}
}
+static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate by IPA. This has to invalidate any structures that
+ * contain only stage 2 translation information, but does not need
+ * to apply to structures that contain combined stage 1 and stage 2
+ * translation information.
+ * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
+ */
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+ uint64_t pageaddr;
+
+ if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
+ return;
+ }
+
+ pageaddr = sextract64(value << 12, 0, 48);
+
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
+}
+
+static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ CPUState *other_cs;
+ uint64_t pageaddr;
+
+ if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
+ return;
+ }
+
+ pageaddr = sextract64(value << 12, 0, 48);
+
+ CPU_FOREACH(other_cs) {
+ tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
+ }
+}
+
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* We don't implement EL2, so the only control on DC ZVA is the
@@ -2889,6 +2928,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
.access = PL1_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_vae1_write },
+ { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1is_write },
+ { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1is_write },
{ .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -2897,6 +2944,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
.access = PL2_W, .type = ARM_CP_NO_RAW,
.writefn = tlbi_aa64_alle1is_write },
+ { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1_write },
+ { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
+ .access = PL2_W, .type = ARM_CP_NO_RAW,
+ .writefn = tlbi_aa64_ipas2e1_write },
{ .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
.access = PL2_W, .type = ARM_CP_NO_RAW,
--
1.9.1
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 19/20] target-arm: Implement missing EL3 TLB invalidate operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs,
Peter Maydell <=
- [Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 01/20] xlnx-zynqmp: Connect the four OCM banks, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 13/20] smbios: add smbios 3.0 support, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 14/20] smbios: implement smbios support for mach-virt, Peter Maydell, 2015/08/25