[Qemu-devel] [RFC PATCH 4/4] hw/intc/arm_gicv3_common: Add vmstate descriptors

[Pavel Fedin]

Add state structure descriptors and actually enable live migration.

Signed-off-by: Pavel Fedin <address@hidden>
---
 hw/intc/arm_gicv3_common.c | 64 +++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 63 insertions(+), 1 deletion(-)

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 0818fb9..71fd9e4 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -44,11 +44,73 @@ static int gicv3_post_load(void *opaque, int version_id)
     return 0;
 }
 
+/* Temporary hack */
+#if __SIZEOF_LONG__ == 8
+#define vmstate_info_ulong vmstate_info_uint64
+#else
+#define vmstate_info_ulong vmstate_info_uint32
+#endif
+
+static const VMStateDescription vmstate_gicv3_irq_state = {
+    .name = "arm_gicv3_irq_state",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_VARRAY_UINT32(enabled, gicv3_irq_state, mask_size, 1,
+                              vmstate_info_ulong, unsigned long),
+        VMSTATE_VARRAY_UINT32(pending, gicv3_irq_state, mask_size, 1,
+                              vmstate_info_ulong, unsigned long),
+        VMSTATE_VARRAY_UINT32(active, gicv3_irq_state, mask_size, 1,
+                              vmstate_info_ulong, unsigned long),
+        VMSTATE_VARRAY_UINT32(level, gicv3_irq_state, mask_size, 1,
+                              vmstate_info_ulong, unsigned long),
+        VMSTATE_VARRAY_UINT32(group, gicv3_irq_state, mask_size, 1,
+                              vmstate_info_ulong, unsigned long),
+        VMSTATE_BOOL(edge_trigger, gicv3_irq_state),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static const VMStateDescription vmstate_gicv3_cpu = {
+    .name = "arm_gicv3_cpu",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_BOOL(cpu_enabled, GICv3CPUState),
+        VMSTATE_UINT8_ARRAY(priority1, GICv3CPUState, GIC_INTERNAL),
+        VMSTATE_UINT64_ARRAY(sgi_pending, GICv3CPUState, GIC_NR_SGIS),
+        VMSTATE_UINT32_ARRAY(ctlr, GICv3CPUState, 2),
+        VMSTATE_UINT32(priority_mask, GICv3CPUState),
+        VMSTATE_UINT32_ARRAY(bpr, GICv3CPUState, 2),
+        VMSTATE_UINT32_2DARRAY(apr, GICv3CPUState, 4, 2),
+        VMSTATE_UINT32(legacy_ctlr, GICv3CPUState),
+        VMSTATE_UINT16(current_pending, GICv3CPUState),
+        VMSTATE_UINT16(running_irq, GICv3CPUState),
+        VMSTATE_UINT16(running_priority, GICv3CPUState),
+        VMSTATE_UINT16_ARRAY(last_active, GICv3CPUState, GICV3_MAXIRQ),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription vmstate_gicv3 = {
     .name = "arm_gicv3",
-    .unmigratable = 1,
+    .version_id = 1,
+    .minimum_version_id = 1,
     .pre_save = gicv3_pre_save,
     .post_load = gicv3_post_load,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(ctlr, GICv3State),
+        VMSTATE_STRUCT_ARRAY(irq_state, GICv3State, GICV3_MAXIRQ, 1,
+                             vmstate_gicv3_irq_state, gicv3_irq_state),
+        VMSTATE_UINT64_ARRAY(irq_route, GICv3State,
+                             GICV3_MAXIRQ - GIC_INTERNAL),
+        VMSTATE_UINT8_ARRAY(priority2, GICv3State,
+                            GICV3_MAXIRQ - GIC_INTERNAL),
+        VMSTATE_UINT64_ARRAY(irq_target, GICv3State, GICV3_MAXIRQ),
+        VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu,
+                                             vmstate_gicv3_cpu, GICv3CPUState),
+        VMSTATE_END_OF_LIST()
+    }
 };
 
 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
-- 
2.4.4