[Qemu-devel] [RFC PATCH 1/4] hw/intc/arm_gicv3_common: Add state information

[Pavel Fedin]

Add state information to GICv3 object structure and implement
arm_gicv3_common_reset(). Also, add some functions for registers which are
not stored directly but simulated.

State information includes not only pure GICv3 data, but also some legacy
registers. This will be useful for implementing software emulation of GICv3
with v2 backwards compatilibity mode.

Signed-off-by: Pavel Fedin <address@hidden>
---
 hw/intc/arm_gicv3_common.c         | 135 +++++++++++++++++++++++++++++++-
 hw/intc/gicv3_internal.h           | 152 +++++++++++++++++++++++++++++++++++++
 include/hw/intc/arm_gicv3_common.h |  76 +++++++++++++++++++
 3 files changed, 362 insertions(+), 1 deletion(-)
 create mode 100644 hw/intc/gicv3_internal.h

diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 032ece2..0818fb9 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -21,6 +21,7 @@
  */
 
 #include "hw/intc/arm_gicv3_common.h"
+#include "gicv3_internal.h"
 
 static void gicv3_pre_save(void *opaque)
 {
@@ -88,6 +89,7 @@ void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler 
handler,
 static void arm_gicv3_common_realize(DeviceState *dev, Error **errp)
 {
     GICv3State *s = ARM_GICV3_COMMON(dev);
+    int i;
 
     /* revision property is actually reserved and currently used only in order
      * to keep the interface compatible with GICv2 code, avoiding extra
@@ -98,11 +100,142 @@ static void arm_gicv3_common_realize(DeviceState *dev, 
Error **errp)
         error_setg(errp, "unsupported GIC revision %d", s->revision);
         return;
     }
+
+    if (s->num_irq > GICV3_MAXIRQ) {
+        error_setg(errp,
+                   "requested %u interrupt lines exceeds GIC maximum %d",
+                   s->num_irq, GICV3_MAXIRQ);
+        return;
+    }
+
+    for (i = 0; i < GICV3_MAXIRQ; i++) {
+        uint32_t mask_size = BITS_TO_LONGS(s->num_cpu);
+
+        s->irq_state[i].mask_size = mask_size;
+        s->irq_state[i].enabled = g_malloc(mask_size * sizeof(unsigned long));
+        s->irq_state[i].pending = g_malloc(mask_size * sizeof(unsigned long));
+        s->irq_state[i].active = g_malloc(mask_size * sizeof(unsigned long));
+        s->irq_state[i].level = g_malloc(mask_size * sizeof(unsigned long));
+        s->irq_state[i].group = g_malloc(mask_size * sizeof(unsigned long));
+    }
+
+    s->cpu = g_malloc(s->num_cpu * sizeof(GICv3CPUState));
 }
 
 static void arm_gicv3_common_reset(DeviceState *dev)
 {
-    /* TODO */
+    GICv3State *s = ARM_GICV3_COMMON(dev);
+    int i;
+
+    for (i = 0; i < s->num_cpu; i++) {
+        GICv3CPUState *c = &s->cpu[i];
+
+        c->cpu_enabled = false;
+        memset(c->priority1, 0, sizeof(c->priority1));
+        memset(c->sgi_pending, 0, sizeof(c->sgi_pending));
+
+        c->ctlr[0] = 0;
+        c->ctlr[1] = 0;
+        c->legacy_ctlr = 0;
+        c->priority_mask = 0;
+        c->bpr[0] = GIC_MIN_BPR0;
+        c->bpr[1] = GIC_MIN_BPR1;
+        memset(c->apr, 0, sizeof(c->apr));
+
+        c->current_pending = 1023;
+        c->running_irq = 1023;
+        c->running_priority = 0x100;
+        memset(c->last_active, 0, sizeof(c->last_active));
+    }
+
+    for (i = 0; i < GICV3_MAXIRQ; i++) {
+        uint32_t mask_size = s->irq_state[i].mask_size;
+
+        memset(s->irq_state[i].enabled, 0, mask_size * sizeof(unsigned long));
+        memset(s->irq_state[i].pending, 0, mask_size * sizeof(unsigned long));
+        memset(s->irq_state[i].active, 0, mask_size * sizeof(unsigned long));
+        memset(s->irq_state[i].level, 0, mask_size * sizeof(unsigned long));
+        memset(s->irq_state[i].group, 0, mask_size * sizeof(unsigned long));
+        s->irq_state[i].edge_trigger = false;
+    }
+
+    /* GIC-500 comment 'j' SGI are always enabled */
+    for (i = 0; i < GIC_NR_SGIS; i++) {
+        set_all_cpus(s, s->irq_state[i].enabled);
+        s->irq_state[i].edge_trigger = true;
+    }
+    /* By default all interrupts always target CPU #0 */
+    for (i = 0; i < GICV3_MAXIRQ; i++) {
+        s->irq_target[i] = 1;
+    }
+    memset(s->irq_route, 0, sizeof(s->irq_route));
+    memset(s->priority2, 0, sizeof(s->priority2));
+
+    /* With all configuration we don't support GICv2 backwards computability */
+    if (s->security_extn) {
+        /* GICv3 5.3.20 With two security So DS is RAZ/WI ARE_NS is RAO/WI
+         * and ARE_S is RAO/WI
+         */
+         s->ctlr = GICD_CTLR_ARE_S | GICD_CTLR_ARE_NS;
+    } else {
+        /* GICv3 5.3.20 With one security So DS is RAO/WI ARE is RAO/WI
+         */
+        s->ctlr = GICD_CTLR_DS | GICD_CTLR_ARE;
+    }
+    /* Workaround!
+     * Linux (drivers/irqchip/irq-gic-v3.c) is enabling only group one,
+     * in gic_cpu_sys_reg_init it calls gic_write_grpen1(1);
+     * but it doesn't conigure any interrupt to be in group one
+     */
+    for (i = 0; i < s->num_irq; i++) {
+        set_all_cpus(s, s->irq_state[i].group);
+    }
+}
+
+void set_irq_bit(GICv3State *s, unsigned long *mask, int irq, int cpu,
+                 bool value)
+{
+    if (irq < GIC_INTERNAL) {
+        if (value) {
+            set_bit(cpu, mask);
+        } else {
+            clear_bit(cpu, mask);
+        }
+    } else {
+        if (value) {
+            set_all_cpus(s, mask);
+        } else {
+            clear_all_cpus(s, mask);
+        }
+    }
+}
+
+uint32_t gicv3_get_igrpen0(GICv3State *s, int cpuindex)
+{
+    GICv3CPUState *c = &s->cpu[cpuindex];
+
+    return extract32(c->legacy_ctlr, GICC_CTLR_EN_GRP0_SHIFT, 1);
+}
+
+void gicv3_set_igrpen0(GICv3State *s, int cpuindex, uint32_t val)
+{
+    GICv3CPUState *c = &s->cpu[cpuindex];
+
+    c->legacy_ctlr = deposit32(c->legacy_ctlr, GICC_CTLR_EN_GRP0_SHIFT, 1, 
val);
+}
+
+uint32_t gicv3_get_igrpen1(GICv3State *s, int cpuindex)
+{
+    GICv3CPUState *c = &s->cpu[cpuindex];
+
+    return extract32(c->legacy_ctlr, GICC_CTLR_EN_GRP1_SHIFT, 1);
+}
+
+void gicv3_set_igrpen1(GICv3State *s, int cpuindex, uint32_t val)
+{
+    GICv3CPUState *c = &s->cpu[cpuindex];
+
+    c->legacy_ctlr = deposit32(c->legacy_ctlr, GICC_CTLR_EN_GRP1_SHIFT, 1, 
val);
 }
 
 static Property arm_gicv3_common_properties[] = {
diff --git a/hw/intc/gicv3_internal.h b/hw/intc/gicv3_internal.h
new file mode 100644
index 0000000..218260f
--- /dev/null
+++ b/hw/intc/gicv3_internal.h
@@ -0,0 +1,152 @@
+/*
+ * ARM GICv3 support - internal interfaces
+ *
+ * Copyright (c) 2012 Linaro Limited
+ * Copyright (c) 2015 Huawei.
+ * Written by Peter Maydell
+ * Adapted to GICv3 by Shlomo Pongratz and Pavel Fedin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_ARM_GICV3_INTERNAL_H
+#define QEMU_ARM_GICV3_INTERNAL_H
+
+#include "hw/intc/arm_gicv3_common.h"
+
+#define GIC_GET_PRIORITY(irq) (((irq) < GIC_INTERNAL) ? c->priority1[irq] : \
+                                    s->priority2[(irq) - GIC_INTERNAL])
+#define GIC_SET_PRIORITY(irq, pri) do { if ((irq) < GIC_INTERNAL) { \
+                                        c->priority1[(irq)] = (pri); } else { \
+                                        s->priority2[(irq) - GIC_INTERNAL] = \
+                                       (pri); } } while (0)
+
+static inline bool gicv3_test_pending(GICv3State *s, int irq, int cpu)
+{
+    /* Edge-triggered interrupts are marked pending on a rising edge, but
+     * level-triggered interrupts are either considered pending when the
+     * level is active or if software has explicitly written to
+     * GICD_ISPENDR to set the state pending.
+     */
+    return test_bit(cpu, s->irq_state[irq].pending) ||
+           (!s->irq_state[irq].edge_trigger &&
+            test_bit(cpu, s->irq_state[irq].level));
+}
+
+static inline void set_all_cpus(GICv3State *s, unsigned long *mask)
+{
+    int i;
+
+    for (i = 0; i < s->num_cpu; i++) {
+        set_bit(i, mask);
+    }
+}
+
+static inline void clear_all_cpus(GICv3State *s, unsigned long *mask)
+{
+    int i;
+
+    for (i = 0; i < s->num_cpu; i++) {
+        clear_bit(i, mask);
+    }
+}
+
+void set_irq_bit(GICv3State *s, unsigned long *mask, int irq, int cpu,
+                 bool value);
+
+#define GICD_CTLR            0x0000
+#define GICD_TYPER           0x0004
+#define GICD_IIDR            0x0008
+#define GICD_STATUSR         0x0010
+#define GICD_SETSPI_NSR      0x0040
+#define GICD_CLRSPI_NSR      0x0048
+#define GICD_SETSPI_SR       0x0050
+#define GICD_CLRSPI_SR       0x0058
+#define GICD_SEIR            0x0068
+#define GICD_IGROUPR         0x0080
+#define GICD_ISENABLER       0x0100
+#define GICD_ICENABLER       0x0180
+#define GICD_ISPENDR         0x0200
+#define GICD_ICPENDR         0x0280
+#define GICD_ISACTIVER       0x0300
+#define GICD_ICACTIVER       0x0380
+#define GICD_IPRIORITYR      0x0400
+#define GICD_ITARGETSR       0x0800
+#define GICD_ICFGR           0x0C00
+#define GICD_CPENDSGIR       0x0F10
+#define GICD_SPENDSGIR       0x0F20
+#define GICD_IROUTER         0x6000
+#define GICD_PIDR2           0xFFE8
+
+/* GICD_CTLR fields  */
+#define GICD_CTLR_EN_GRP0           (1U << 0)
+#define GICD_CTLR_EN_GRP1NS         (1U << 1) /* GICv3 5.3.20 */
+#define GICD_CTLR_EN_GRP1S          (1U << 2)
+#define GICD_CTLR_EN_GRP1_ALL       (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S)
+#define GICD_CTLR_ARE               (1U << 4)
+#define GICD_CTLR_ARE_S             (1U << 4)
+#define GICD_CTLR_ARE_NS            (1U << 5)
+#define GICD_CTLR_DS                (1U << 6)
+#define GICD_CTLR_RWP               (1U << 31)
+
+/*
+ * Redistributor frame offsets from RD_base
+ */
+#define GICR_SGI_OFFSET 0x10000
+
+/*
+ * Re-Distributor registers, offsets from RD_base
+ */
+#define GICR_CTLR             GICD_CTLR
+#define GICR_IIDR             0x0004
+#define GICR_TYPER            0x0008
+#define GICR_STATUSR          GICD_STATUSR
+#define GICR_WAKER            0x0014
+#define GICR_SETLPIR          0x0040
+#define GICR_CLRLPIR          0x0048
+#define GICR_SEIR             GICD_SEIR
+#define GICR_PROPBASER        0x0070
+#define GICR_PENDBASER        0x0078
+#define GICR_INVLPIR          0x00A0
+#define GICR_INVALLR          0x00B0
+#define GICR_SYNCR            0x00C0
+#define GICR_MOVLPIR          0x0100
+#define GICR_MOVALLR          0x0110
+#define GICR_PIDR2            GICD_PIDR2
+
+#define GICR_WAKER_ProcessorSleep    (1U << 1)
+#define GICR_WAKER_ChildrenAsleep    (1U << 2)
+
+/*
+ * Simulated used system registers
+ */
+#define GICC_CTLR_EN_GRP0_SHIFT 0
+#define GICC_CTLR_EN_GRP0       (1U << GICC_CTLR_EN_GRP0_SHIFT)
+#define GICC_CTLR_EN_GRP1_SHIFT 1
+#define GICC_CTLR_EN_GRP1       (1U << GICC_CTLR_EN_GRP1_SHIFT)
+#define GICC_CTLR_ACK_CTL       (1U << 2)
+#define GICC_CTLR_FIQ_EN        (1U << 3)
+#define GICC_CTLR_CBPR          (1U << 4) /* GICv1: SBPR */
+#define GICC_CTLR_EOIMODE       (1U << 9)
+#define GICC_CTLR_EOIMODE_NS    (1U << 10)
+
+#define ICC_CTLR_CBPR           (1U << 0)
+#define ICC_CTLR_EOIMODE        (1U << 1)
+#define ICC_CTLR_PMHE           (1U << 6)
+
+#define ICC_PMR_PRIORITY_MASK    0xff
+#define ICC_BPR_BINARYPOINT_MASK 0x07
+#define ICC_IGRPEN_ENABLE        0x01
+
+#endif /* !QEMU_ARM_GIC_INTERNAL_H */
diff --git a/include/hw/intc/arm_gicv3_common.h 
b/include/hw/intc/arm_gicv3_common.h
index c2fd8da..b372566 100644
--- a/include/hw/intc/arm_gicv3_common.h
+++ b/include/hw/intc/arm_gicv3_common.h
@@ -26,6 +26,60 @@
 #include "hw/sysbus.h"
 #include "hw/intc/arm_gic_common.h"
 
+/*
+ * Maximum number of possible interrupts, determined by the GIC architecture.
+ * Note that this does not include LPIs. When implemented, these should be
+ * dealt with separately.
+ */
+#define GICV3_MAXIRQ 1020
+
+#define GIC_MIN_BPR0 0
+#define GIC_MIN_BPR1 (GIC_MIN_BPR0 + 1)
+
+struct gicv3_irq_state {
+    /* The enable bits are only banked for per-cpu interrupts.  */
+    unsigned long *enabled;
+    unsigned long *pending;
+    unsigned long *active;
+    unsigned long *level;
+    unsigned long *group;
+    bool edge_trigger; /* true: edge-triggered, false: level-triggered  */
+    uint32_t mask_size; /* Size of bitfields in long's, for migration */
+};
+
+typedef struct gicv3_irq_state gicv3_irq_state;
+
+struct GICv3CPUState {
+    /* Redistributor */
+    bool cpu_enabled;                /* !GICR_WAKER_ProcessorSleep */
+    uint8_t priority1[GIC_INTERNAL]; /* GICR_IPRIORITYR */
+
+    /* CPU interface */
+    uint32_t ctlr[2];                /* ICC_CTLR_EL1, banked */
+    uint32_t priority_mask;          /* ICC_PMR_EL1 */
+    uint32_t bpr[2];
+    uint32_t apr[4][2];
+
+    /* Legacy CPU interface */
+    uint32_t legacy_ctlr;            /* GICC_CTLR */
+    /* For each SGI on the target CPU, we store bit mask
+     * indicating which source CPUs have made this SGI
+     * pending on the target CPU. These correspond to
+     * the bytes in the GIC_SPENDSGIR* registers as
+     * read by the target CPU.
+     */
+    uint64_t sgi_pending[GIC_NR_SGIS];
+
+    /* Internal state */
+
+    uint16_t current_pending;
+    uint16_t running_irq;
+    uint16_t running_priority;
+    uint16_t last_active[GICV3_MAXIRQ];
+};
+
+typedef struct GICv3CPUState GICv3CPUState;
+
 typedef struct GICv3State {
     /*< private >*/
     SysBusDevice parent_obj;
@@ -43,6 +97,22 @@ typedef struct GICv3State {
     bool security_extn;
 
     int dev_fd; /* kvm device fd if backed by kvm vgic support */
+
+    /* Distributor */
+
+    /* GICD_CTLR; for a GIC with the security extensions the NS banked version
+     * of this register is just an alias of bit 1 of the S banked version.
+     */
+    uint32_t ctlr;
+
+    gicv3_irq_state irq_state[GICV3_MAXIRQ];
+    uint64_t irq_route[GICV3_MAXIRQ - GIC_INTERNAL]; /* GICD_IROUTER */
+    uint8_t priority2[GICV3_MAXIRQ - GIC_INTERNAL];
+
+    /* Legacy distributor */
+    uint64_t irq_target[GICV3_MAXIRQ];
+
+    GICv3CPUState *cpu;
 } GICv3State;
 
 #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common"
@@ -65,4 +135,10 @@ typedef struct ARMGICv3CommonClass {
 void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler,
                               const MemoryRegionOps *ops);
 
+/* Accessors for simulated system registers */
+uint32_t gicv3_get_igrpen0(GICv3State *s, int cpuindex);
+void gicv3_set_igrpen0(GICv3State *s, int cpuindex, uint32_t val);
+uint32_t gicv3_get_igrpen1(GICv3State *s, int cpuindex);
+void gicv3_set_igrpen1(GICv3State *s, int cpuindex, uint32_t val);
+
 #endif
-- 
2.4.4