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[Qemu-devel] [PATCH v2] target-tilegx: Support iret instruction and rela
From: |
gang . chen . 5i5j |
Subject: |
[Qemu-devel] [PATCH v2] target-tilegx: Support iret instruction and related special registers |
Date: |
Thu, 1 Oct 2015 19:01:26 +0800 |
From: Chen Gang <address@hidden>
Acording to the __longjmp tilegx libc implementation, and reference from
tilegx ISA document, we can left iret instruction empty. The related
code is below:
ENTRY (__longjmp)
FEEDBACK_ENTER(__longjmp)
#define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE }
FOR_EACH_CALLEE_SAVED_REG(RESTORE)
{
LD r2, r0 ; retrieve ICS bit from jmp_buf
movei r3, 1
CMPEQI r0, r1, 0
}
{
mtspr INTERRUPT_CRITICAL_SECTION, r3
shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT
}
{
mtspr EX_CONTEXT_0_0, lr
ori r2, r2, RETURN_PL
}
{
or r0, r1, r0
mtspr EX_CONTEXT_0_1, r2
}
iret
jrp lr
Until now, EX_CONTEXT_0_0 and EX_CONTEXT_0_1 are only used in mtspr, so
just skip them, at present.
After this patch, busybox sh can run correctly.
Signed-off-by: Chen Gang <address@hidden>
---
target-tilegx/translate.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index 421766b..3ae59fe 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -563,8 +563,10 @@ static TileExcp gen_rr_opcode(DisasContext *dc, unsigned
opext,
break;
case OE_RR_X0(FSINGLE_PACK1):
case OE_RR_Y0(FSINGLE_PACK1):
- case OE_RR_X1(IRET):
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+ case OE_RR_X1(IRET):
+ mnemonic = "iret";
+ break;
case OE_RR_X1(LD1S):
memop = MO_SB;
mnemonic = "ld1s"; /* prefetch_l1_fault */
@@ -1823,6 +1825,8 @@ static const TileSPR *find_spr(unsigned spr)
offsetof(CPUTLGState, spregs[TILEGX_SPR_CRITICAL_SEC]), 0, 0)
D(SIM_CONTROL,
offsetof(CPUTLGState, spregs[TILEGX_SPR_SIM_CONTROL]), 0, 0)
+ D(EX_CONTEXT_0_0, -1, 0, 0) /* Skip it */
+ D(EX_CONTEXT_0_1, -1, 0, 0) /* Skip it */
}
#undef D
@@ -1836,9 +1840,11 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned
spr, unsigned srca)
const TileSPR *def = find_spr(spr);
TCGv tsrca;
- if (def == NULL) {
+ if (!def) {
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr spr[%u], %s", spr,
reg_names[srca]);
return TILEGX_EXCP_OPCODE_UNKNOWN;
+ } else if (def->offset == -1) {
+ goto tail;
}
tsrca = load_gr(dc, srca);
@@ -1847,6 +1853,8 @@ static TileExcp gen_mtspr_x1(DisasContext *dc, unsigned
spr, unsigned srca)
} else {
tcg_gen_st_tl(tsrca, cpu_env, def->offset);
}
+
+tail:
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, %s", def->name,
reg_names[srca]);
return TILEGX_EXCP_NONE;
}
@@ -1856,7 +1864,7 @@ static TileExcp gen_mfspr_x1(DisasContext *dc, unsigned
dest, unsigned spr)
const TileSPR *def = find_spr(spr);
TCGv tdest;
- if (def == NULL) {
+ if (!def || def->offset == -1) {
qemu_log_mask(CPU_LOG_TB_IN_ASM, "mtspr %s, spr[%u]", reg_names[dest],
spr);
return TILEGX_EXCP_OPCODE_UNKNOWN;
}
--
1.9.3
- [Qemu-devel] [PATCH v2] target-tilegx: Support iret instruction and related special registers,
gang . chen . 5i5j <=