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[Qemu-devel] [PULL 13/27] i.MX: Standardize i.MX GPT debug
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/27] i.MX: Standardize i.MX GPT debug |
Date: |
Tue, 27 Oct 2015 14:33:15 +0000 |
From: Jean-Christophe Dubois <address@hidden>
The goal is to have debug code always compiled during build.
We standardize all debug output on the following format:
[QOM_TYPE_NAME]reporting_function: debug message
We also replace IPRINTF with qemu_log_mask(). The qemu_log_mask() output
is following the same format as the above debug.
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Jean-Christophe Dubois <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/timer/imx_gpt.c | 56 ++++++++++++++++++++++--------------------------------
1 file changed, 23 insertions(+), 33 deletions(-)
diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 4bac67d..7257f42 100644
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -16,11 +16,17 @@
#include "hw/misc/imx_ccm.h"
#include "qemu/main-loop.h"
-/*
- * Define to 1 for debug messages
- */
-#define DEBUG_TIMER 0
-#if DEBUG_TIMER
+#ifndef DEBUG_IMX_GPT
+#define DEBUG_IMX_GPT 0
+#endif
+
+#define DPRINTF(fmt, args...) \
+ do { \
+ if (DEBUG_IMX_GPT) { \
+ fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
+ __func__, ##args); \
+ } \
+ } while (0)
static char const *imx_gpt_reg_name(uint32_t reg)
{
@@ -50,24 +56,6 @@ static char const *imx_gpt_reg_name(uint32_t reg)
}
}
-# define DPRINTF(fmt, args...) \
- do { printf("%s: " fmt , __func__, ##args); } while (0)
-#else
-# define DPRINTF(fmt, args...) do {} while (0)
-#endif
-
-/*
- * Define to 1 for messages about attempts to
- * access unimplemented registers or similar.
- */
-#define DEBUG_IMPLEMENTATION 1
-#if DEBUG_IMPLEMENTATION
-# define IPRINTF(fmt, args...) \
- do { fprintf(stderr, "%s: " fmt, __func__, ##args); } while (0)
-#else
-# define IPRINTF(fmt, args...) do {} while (0)
-#endif
-
static const VMStateDescription vmstate_imx_timer_gpt = {
.name = TYPE_IMX_GPT,
.version_id = 3,
@@ -224,9 +212,8 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset,
unsigned size)
{
IMXGPTState *s = IMX_GPT(opaque);
uint32_t reg_value = 0;
- uint32_t reg = offset >> 2;
- switch (reg) {
+ switch (offset >> 2) {
case 0: /* Control Register */
reg_value = s->cr;
break;
@@ -256,12 +243,14 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset,
unsigned size)
break;
case 7: /* input Capture Register 1 */
- qemu_log_mask(LOG_UNIMP, "icr1 feature is not implemented\n");
+ qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
+ TYPE_IMX_GPT, __func__);
reg_value = s->icr1;
break;
case 8: /* input Capture Register 2 */
- qemu_log_mask(LOG_UNIMP, "icr2 feature is not implemented\n");
+ qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
+ TYPE_IMX_GPT, __func__);
reg_value = s->icr2;
break;
@@ -271,11 +260,12 @@ static uint64_t imx_gpt_read(void *opaque, hwaddr offset,
unsigned size)
break;
default:
- IPRINTF("Bad offset %x\n", reg);
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
break;
}
- DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(reg), reg_value);
+ DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
return reg_value;
}
@@ -322,12 +312,11 @@ static void imx_gpt_write(void *opaque, hwaddr offset,
uint64_t value,
{
IMXGPTState *s = IMX_GPT(opaque);
uint32_t oldreg;
- uint32_t reg = offset >> 2;
- DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(reg),
+ DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
(uint32_t)value);
- switch (reg) {
+ switch (offset >> 2) {
case 0:
oldreg = s->cr;
s->cr = value & ~0x7c14;
@@ -403,7 +392,8 @@ static void imx_gpt_write(void *opaque, hwaddr offset,
uint64_t value,
break;
default:
- IPRINTF("Bad offset %x\n", reg);
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
+ HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
break;
}
}
--
1.9.1
- [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 25/27] target-arm: Add S2 translation to 32bit S1 PTWs, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 17/27] target-arm: Add support for AArch32 S2 negative t0sz, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 26/27] target-arm: Route S2 MMU faults to EL2, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 14/27] target-arm: Add HPFAR_EL2, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 13/27] i.MX: Standardize i.MX GPT debug,
Peter Maydell <=
- [Qemu-devel] [PULL 19/27] target-arm: lpae: Rename granule_sz to stride, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 23/27] target-arm: Add ARMMMUFaultInfo, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 24/27] target-arm: Add S2 translation to 64bit S1 PTWs, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 16/27] target-arm: lpae: Move declaration of t0sz and t1sz, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 21/27] target-arm: Add support for S2 page-table protection bits, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked(), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 10/27] i.MX: Standardize i.MX CCM debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 05/27] hw/arm/virt: don't use a15memmap directly, Peter Maydell, 2015/10/27