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[Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked() |
Date: |
Tue, 27 Oct 2015 14:33:03 +0000 |
The code in arm_excp_unmasked() suppresses the ability of PSTATE.AIF
to mask exceptions from a lower EL targeting EL2 or EL3 if the
CPU is 64-bit. This is correct for a target of EL3, but not correct
for targeting EL2. Further, we go to some effort to calculate
scr and hcr values which are not used at all for the 64-bit CPU
case.
Rearrange the code to correctly implement the 64-bit CPU logic
and keep the hcr/scr calculations in the 32-bit CPU codepath.
Signed-off-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 82 +++++++++++++++++++++++++++++++++++---------------------
1 file changed, 52 insertions(+), 30 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3daa7f5..a271205 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1525,8 +1525,6 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_el(env);
bool secure = arm_is_secure(env);
- bool scr;
- bool hcr;
bool pstate_unmasked;
int8_t unmasked = 0;
@@ -1540,31 +1538,10 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
switch (excp_idx) {
case EXCP_FIQ:
- /* If FIQs are routed to EL3 or EL2 then there are cases where we
- * override the CPSR.F in determining if the exception is masked or
- * not. If neither of these are set then we fall back to the CPSR.F
- * setting otherwise we further assess the state below.
- */
- hcr = (env->cp15.hcr_el2 & HCR_FMO);
- scr = (env->cp15.scr_el3 & SCR_FIQ);
-
- /* When EL3 is 32-bit, the SCR.FW bit controls whether the CPSR.F bit
- * masks FIQ interrupts when taken in non-secure state. If SCR.FW is
- * set then FIQs can be masked by CPSR.F when non-secure but only
- * when FIQs are only routed to EL3.
- */
- scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
pstate_unmasked = !(env->daif & PSTATE_F);
break;
case EXCP_IRQ:
- /* When EL3 execution state is 32-bit, if HCR.IMO is set then we may
- * override the CPSR.I masking when in non-secure state. The SCR.IRQ
- * setting has already been taken into consideration when setting the
- * target EL, so it does not have a further affect here.
- */
- hcr = (env->cp15.hcr_el2 & HCR_IMO);
- scr = false;
pstate_unmasked = !(env->daif & PSTATE_I);
break;
@@ -1589,13 +1566,58 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx,
* interrupt.
*/
if ((target_el > cur_el) && (target_el != 1)) {
- /* ARM_FEATURE_AARCH64 enabled means the highest EL is AArch64.
- * This code currently assumes that EL2 is not implemented
- * (and so that highest EL will be 3 and the target_el also 3).
- */
- if (arm_feature(env, ARM_FEATURE_AARCH64) ||
- ((scr || hcr) && (!secure))) {
- unmasked = 1;
+ /* Exceptions targeting a higher EL may not be maskable */
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
+ /* 64-bit masking rules are simple: exceptions to EL3
+ * can't be masked, and exceptions to EL2 can only be
+ * masked from Secure state. The HCR and SCR settings
+ * don't affect the masking logic, only the interrupt routing.
+ */
+ if (target_el == 3 || !secure) {
+ unmasked = 1;
+ }
+ } else {
+ /* The old 32-bit-only environment has a more complicated
+ * masking setup. HCR and SCR bits not only affect interrupt
+ * routing but also change the behaviour of masking.
+ */
+ bool hcr, scr;
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ /* If FIQs are routed to EL3 or EL2 then there are cases where
+ * we override the CPSR.F in determining if the exception is
+ * masked or not. If neither of these are set then we fall back
+ * to the CPSR.F setting otherwise we further assess the state
+ * below.
+ */
+ hcr = (env->cp15.hcr_el2 & HCR_FMO);
+ scr = (env->cp15.scr_el3 & SCR_FIQ);
+
+ /* When EL3 is 32-bit, the SCR.FW bit controls whether the
+ * CPSR.F bit masks FIQ interrupts when taken in non-secure
+ * state. If SCR.FW is set then FIQs can be masked by CPSR.F
+ * when non-secure but only when FIQs are only routed to EL3.
+ */
+ scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
+ break;
+ case EXCP_IRQ:
+ /* When EL3 execution state is 32-bit, if HCR.IMO is set then
+ * we may override the CPSR.I masking when in non-secure state.
+ * The SCR.IRQ setting has already been taken into
consideration
+ * when setting the target EL, so it does not have a further
+ * affect here.
+ */
+ hcr = (env->cp15.hcr_el2 & HCR_IMO);
+ scr = false;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if ((scr || hcr) && !secure) {
+ unmasked = 1;
+ }
}
}
--
1.9.1
- [Qemu-devel] [PULL 17/27] target-arm: Add support for AArch32 S2 negative t0sz, (continued)
- [Qemu-devel] [PULL 17/27] target-arm: Add support for AArch32 S2 negative t0sz, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 26/27] target-arm: Route S2 MMU faults to EL2, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 14/27] target-arm: Add HPFAR_EL2, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 13/27] i.MX: Standardize i.MX GPT debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 19/27] target-arm: lpae: Rename granule_sz to stride, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 23/27] target-arm: Add ARMMMUFaultInfo, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 24/27] target-arm: Add S2 translation to 64bit S1 PTWs, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 16/27] target-arm: lpae: Move declaration of t0sz and t1sz, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 21/27] target-arm: Add support for S2 page-table protection bits, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked(),
Peter Maydell <=
- [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 10/27] i.MX: Standardize i.MX CCM debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 05/27] hw/arm/virt: don't use a15memmap directly, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 03/27] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 04/27] arm_gic_kvm: Disable live migration if not supported, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed integers, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 18/27] target-arm: lpae: Replace tsz with computed inputsize, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug., Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 22/27] target-arm: Avoid inline for get_phys_addr, Peter Maydell, 2015/10/27