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[Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6 |
Date: |
Fri, 30 Oct 2015 15:00:46 +0000 |
Implement the relationship between CP0.Status.KX, SX and UX. It should not
be possible to set UX bit if SX is 0, the same applies for setting SX if
KX is 0.
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/cpu.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3799d26..c68681d 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -1001,7 +1001,12 @@ static inline void cpu_mips_store_status(CPUMIPSState
*env, target_ulong val)
if (env->insn_flags & ISA_MIPS32R6) {
bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3;
-
+#if defined(TARGET_MIPS64)
+ uint32_t ksux = (1 << CP0St_KX) & val;
+ ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */
+ ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */
+ val = (val & ~(7 << CP0St_UX)) | ksux;
+#endif
if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) {
mask &= ~(3 << CP0St_KSU);
}
--
2.1.0
- [Qemu-devel] [PULL 0/9] target-mips queue, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 1/9] target-mips: move the test for enabled interrupts to a separate function, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 5/9] hw/mips_malta: Fix KVM PC initialisation, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 9/9] target-mips: fix updating XContext on mmu exception, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 2/9] target-mips: implement the CPU wake-up on non-enabled interrupts in R6, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 6/9] target-mips: add PC, XNP reg numbers to RDHWR, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 3/9] target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6,
Leon Alrae <=
- [Qemu-devel] [PULL 4/9] target-mips: Add enum for BREAK32, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 7/9] target-mips: Set Config5.XNP for R6 cores, Leon Alrae, 2015/10/30
- [Qemu-devel] [PULL 8/9] target-mips: add SIGRIE instruction, Leon Alrae, 2015/10/30
- Re: [Qemu-devel] [PULL 0/9] target-mips queue, Peter Maydell, 2015/10/30