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Re: [Qemu-devel] [PATCH 15/15] tcg-mips: Use mipsr6 instructions in call


From: James Hogan
Subject: Re: [Qemu-devel] [PATCH 15/15] tcg-mips: Use mipsr6 instructions in calls
Date: Wed, 10 Feb 2016 12:49:15 +0000
User-agent: Mutt/1.5.23 (2014-03-12)

Hi Richard,

On Tue, Feb 09, 2016 at 09:40:03PM +1100, Richard Henderson wrote:
> @@ -1313,28 +1315,30 @@ static void tcg_out_movcond(TCGContext *s, TCGCond 
> cond, TCGReg ret,
>      }
>  }
>  
> -static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
> +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg,
> +                             bool tail, bool delay)
>  {
>      /* Note that the ABI requires the called function's address to be
>         loaded into T9, even if a direct branch is in range.  */
>      tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
>  
>      /* But do try a direct branch, allowing the cpu better insn prefetch.  */
> -    if (tail) {
> -        if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
> -            tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
> -        }
> +    if (tcg_out_opc_jmp(s, tail ? OPC_J : OPC_JAL, arg)) {
> +        if (!delay) {
> +            tcg_out_nop(s);
> +        }
> +    } else if (use_mips32r6_instructions && !delay) {
> +        tcg_out_opc_reg(s, tail ? OPC_JIC : OPC_JIALC, 0, TCG_REG_T9, 0);

this needs to be "...JIALC, 0, 0, TCG_REG_T9);" to get t9 into rt.

Cheers
James

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