[Qemu-devel] [PATCH v3 0/4] Added 5 instructions to the tricore target

[peer . adelt]

From: Peer Adelt <address@hidden>

This patch set contains 5 new instructions:
 - FTOUZ (converts float to unsigned int, rounds towards zero)
 - MADD.F / MSUB.F (multiplies two floats and adds/subtracts result
                    to/from the third operand)
 - MOV (new variant in RR format - see ISA v1.6 for details)
 - JNE (new variant in SBC format - see ISA v1.6 for details)

v3:
  PATCH 1/4: target-tricore: Added FTOUZ instruction
  - Removed unnecessary cast

  PATCH 2/4: target-tricore: Added MADD.F and MSUB.F instructions
  - Provided correct negation options for float32_muladd()
    instead of negating one of the input arguments
  - Calculate NaN results as required in the datasheet

  PATCH 3/4: target-tricore: Added new MOV instruction variant
  - Removed unnecessary parentheses
  - Used temp register to avoid losing the value of r1
  - Checks that r3+1:r3 for a valid 64 Bit extended register

  PATCH 4/4: target-tricore: Added new JNE instruction variant
  - gen_compute_branch() now calculates the displacement value

v2:
  PATCH 3/4: target-tricore: Added new MOV instruction variant
  - Checks TriCore ISA version requirement

  PATCH 4/4: target-tricore: Added new JNE instruction variant
  - Checks TriCore ISA version requirement


Peer Adelt (4):
  target-tricore: Added FTOUZ instruction
  target-tricore: Added MADD.F and MSUB.F instructions
  target-tricore: Added new MOV instruction variant
  target-tricore: Added new JNE instruction variant

 target-tricore/fpu_helper.c      | 77 ++++++++++++++++++++++++++++++++++++++++
 target-tricore/helper.h          |  3 ++
 target-tricore/translate.c       | 42 ++++++++++++++++++++++
 target-tricore/tricore-opcodes.h |  3 ++
 4 files changed, 125 insertions(+)

-- 
2.7.4