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[Qemu-devel] [PATCH 14/25] target-openrisc: Implement muld, muldu, macu,
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 14/25] target-openrisc: Implement muld, muldu, macu, msbu |
Date: |
Mon, 13 Jun 2016 16:58:14 -0700 |
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-openrisc/translate.c | 106 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 106 insertions(+)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index d028612..4ce51ea 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -347,6 +347,54 @@ static void gen_divu(DisasContext *dc, TCGv dest, TCGv
srca, TCGv srcb)
gen_ove_cy(dc);
}
+static void gen_muld(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_ext_tl_i64(t1, srca);
+ tcg_gen_ext_tl_i64(t2, srcb);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_gen_mul_i64(cpu_mac, t1, t2);
+ } else {
+ TCGv_i64 high = tcg_temp_new_i64();
+
+ tcg_gen_muls2_i64(cpu_mac, high, t1, t2);
+ tcg_gen_sari_i64(t1, cpu_mac, 63);
+ tcg_gen_setcond_i64(TCG_COND_NE, t1, t1, high);
+ tcg_temp_free_i64(high);
+ tcg_gen_trunc_i64_tl(cpu_sr_ov, t1);
+ tcg_gen_neg_tl(cpu_sr_ov, cpu_sr_ov);
+
+ gen_ove_ov(dc);
+ }
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
+static void gen_muldu(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(t1, srca);
+ tcg_gen_extu_tl_i64(t2, srcb);
+ if (TARGET_LONG_BITS == 32) {
+ tcg_gen_mul_i64(cpu_mac, t1, t2);
+ } else {
+ TCGv_i64 high = tcg_temp_new_i64();
+
+ tcg_gen_mulu2_i64(cpu_mac, high, t1, t2);
+ tcg_gen_setcondi_i64(TCG_COND_NE, high, high, 0);
+ tcg_gen_trunc_i64_tl(cpu_sr_cy, high);
+ tcg_temp_free_i64(high);
+
+ gen_ove_cy(dc);
+ }
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+
static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb)
{
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -373,6 +421,25 @@ static void gen_mac(DisasContext *dc, TCGv srca, TCGv srcb)
gen_ove_ov(dc);
}
+static void gen_macu(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(t1, srca);
+ tcg_gen_extu_tl_i64(t2, srcb);
+ tcg_gen_mul_i64(t1, t1, t2);
+ tcg_temp_free_i64(t2);
+
+ /* Note that overflow is only computed during addition stage. */
+ tcg_gen_add_i64(cpu_mac, cpu_mac, t1);
+ tcg_gen_setcond_i64(TCG_COND_LTU, t1, cpu_mac, t1);
+ tcg_gen_trunc_i64_tl(cpu_sr_cy, t1);
+ tcg_temp_free_i64(t1);
+
+ gen_ove_cy(dc);
+}
+
static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb)
{
TCGv_i64 t1 = tcg_temp_new_i64();
@@ -399,6 +466,25 @@ static void gen_msb(DisasContext *dc, TCGv srca, TCGv srcb)
gen_ove_ov(dc);
}
+static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
+{
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(t1, srca);
+ tcg_gen_extu_tl_i64(t2, srcb);
+ tcg_gen_mul_i64(t1, t1, t2);
+
+ /* Note that overflow is only computed during subtraction stage. */
+ tcg_gen_setcond_i64(TCG_COND_LTU, t2, cpu_mac, t1);
+ tcg_gen_sub_i64(cpu_mac, cpu_mac, t1);
+ tcg_gen_trunc_i64_tl(cpu_sr_cy, t2);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t1);
+
+ gen_ove_cy(dc);
+}
+
static void dec_calc(DisasContext *dc, uint32_t insn)
{
uint32_t op0, op1, op2;
@@ -534,6 +620,11 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
gen_mul(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]);
return;
+ case 0x7: /* l.muld */
+ LOG_DIS("l.muld r%d, r%d\n", ra, rb);
+ gen_muld(dc, cpu_R[ra], cpu_R[rb]);
+ break;
+
case 0x9: /* l.div */
LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
gen_div(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]);
@@ -548,6 +639,11 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb);
gen_mulu(dc, cpu_R[rd], cpu_R[ra], cpu_R[rb]);
return;
+
+ case 0xc: /* l.muldu */
+ LOG_DIS("l.muldu r%d, r%d\n", ra, rb);
+ gen_muldu(dc, cpu_R[ra], cpu_R[rb]);
+ return;
}
break;
}
@@ -818,6 +914,16 @@ static void dec_mac(DisasContext *dc, uint32_t insn)
gen_msb(dc, cpu_R[ra], cpu_R[rb]);
break;
+ case 0x0003: /* l.macu */
+ LOG_DIS("l.macu r%d, r%d\n", ra, rb);
+ gen_macu(dc, cpu_R[ra], cpu_R[rb]);
+ break;
+
+ case 0x0004: /* l.msbu */
+ LOG_DIS("l.msbu r%d, r%d\n", ra, rb);
+ gen_msbu(dc, cpu_R[ra], cpu_R[rb]);
+ break;
+
default:
gen_illegal_exception(dc);
break;
--
2.5.5
- [Qemu-devel] [PATCH 06/25] target-openrisc: Put SR[OVE] in TB flags, (continued)
- [Qemu-devel] [PATCH 06/25] target-openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 05/25] target-openrisc: Use movcond where appropriate, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 08/25] target-openrisc: Set flags on helpers, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 03/25] target-openrisc: Invert the decoding in dec_calc, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 04/25] target-openrisc: Keep SR_F in a separate variable, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 07/25] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 02/25] target-openrisc: Streamline arithmetic and OVE, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 12/25] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 11/25] target-openrisc: Rationalize immediate extraction, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 14/25] target-openrisc: Implement muld, muldu, macu, msbu,
Richard Henderson <=
- [Qemu-devel] [PATCH 19/25] target-openrisc: Tidy ppc/npc implementation, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 09/25] target-openrisc: Implement ff1 and fl1 for 64-bit, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 21/25] target-openrisc: Tidy insn dumping, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 16/25] target-openrisc: Write back result before FPE exception, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 18/25] target-openrisc: Implement l.adrp, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 20/25] target-openrisc: Optimize l.jal to next, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 10/25] target-openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 17/25] target-openrisc: Implement lwa, swa, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 15/25] target-openrisc: Fix madd, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 24/25] target-openrisc: Generate goto_tb for direct branches, Richard Henderson, 2016/06/13