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[Qemu-devel] [PATCH 21/25] target-openrisc: Tidy insn dumping
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 21/25] target-openrisc: Tidy insn dumping |
Date: |
Mon, 13 Jun 2016 16:58:21 -0700 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-openrisc/translate.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 31f4307..3102190 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -36,7 +36,8 @@
/* Set to 0 to completely disable. */
#define OPENRISC_DISAS CPU_LOG_TB_IN_ASM
-#define LOG_DIS(...) qemu_log_mask(OPENRISC_DISAS, ## __VA_ARGS__)
+#define LOG_DIS(str, ...) \
+ qemu_log_mask(OPENRISC_DISAS, "%08x: " str, dc->pc, ## __VA_ARGS__)
typedef struct DisasContext {
TranslationBlock *tb;
@@ -1511,9 +1512,9 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct
TranslationBlock *tb)
dc->synced_flags = dc->tb_flags = tb->flags;
dc->delayed_branch = (dc->tb_flags & D_FLAG) != 0;
dc->singlestep_enabled = cs->singlestep_enabled;
+
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
- qemu_log("-----------------------------------------\n");
- log_cpu_state(CPU(cpu), 0);
+ qemu_log("IN: %s\n", lookup_symbol(pc_start));
}
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
--
2.5.5
- [Qemu-devel] [PATCH 03/25] target-openrisc: Invert the decoding in dec_calc, (continued)
- [Qemu-devel] [PATCH 03/25] target-openrisc: Invert the decoding in dec_calc, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 04/25] target-openrisc: Keep SR_F in a separate variable, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 07/25] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 02/25] target-openrisc: Streamline arithmetic and OVE, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 12/25] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, psync for user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 11/25] target-openrisc: Rationalize immediate extraction, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 14/25] target-openrisc: Implement muld, muldu, macu, msbu, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 19/25] target-openrisc: Tidy ppc/npc implementation, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 09/25] target-openrisc: Implement ff1 and fl1 for 64-bit, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 21/25] target-openrisc: Tidy insn dumping,
Richard Henderson <=
- [Qemu-devel] [PATCH 16/25] target-openrisc: Write back result before FPE exception, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 18/25] target-openrisc: Implement l.adrp, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 20/25] target-openrisc: Optimize l.jal to next, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 10/25] target-openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 17/25] target-openrisc: Implement lwa, swa, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 15/25] target-openrisc: Fix madd, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 24/25] target-openrisc: Generate goto_tb for direct branches, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 25/25] target-openrisc: Generate goto_tb for conditional branches, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 22/25] target-openrisc: Tidy handling of delayed branches, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 23/25] target-openrisc: Optimize for r0 being zero, Richard Henderson, 2016/06/13