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Re: [Qemu-devel] [PULL v5 26/57] x86-iommu: introduce IEC notifiers
From: |
Peter Xu |
Subject: |
Re: [Qemu-devel] [PULL v5 26/57] x86-iommu: introduce IEC notifiers |
Date: |
Sun, 31 Jul 2016 20:51:51 +0800 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Sun, Jul 31, 2016 at 02:01:26PM +0200, Jan Kiszka wrote:
[...]
> Yes, there has to be a generic handle for each translation result an
> IOMMU generated. This handle can be stored on the consumer side along
> with the translation request. How a handle is generated should be
> completely up to the IOMMU.
>
> The consumer should receive a 32-bit (or more) opaque value with each
> translation request (separate parameter) and then again on specific
> invalidation. The latter case may also report a range of handles, to
> make things more efficient (provided the consumer store those handles
> close to each other).
Agreed. So I think masking can still survive to describe "a range of
handles" for AMD IOMMUs, as long as we are sure the masked range
covers the maximum index number of IRTE entry for specific device.
Thanks,
-- peterx
- [Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defines, (continued)
- [Qemu-devel] [PULL v5 20/57] intel_iommu: add IR translation faults defines, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 21/57] intel_iommu: Add support for PCI MSI remap, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 22/57] intel_iommu: get rid of {0} initializers, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 23/57] q35: ioapic: add support for emulated IOAPIC IR, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 24/57] ioapic: introduce ioapic_entry_parse() helper, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 25/57] intel_iommu: add support for split irqchip, Michael S. Tsirkin, 2016/07/21
- [Qemu-devel] [PULL v5 26/57] x86-iommu: introduce IEC notifiers, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 27/57] ioapic: register IOMMU IEC notifier for ioapic, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 28/57] intel_iommu: Add support for Extended Interrupt Mode, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 29/57] intel_iommu: add SID validation for IR, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 30/57] kvm-irqchip: simplify kvm_irqchip_add_msi_route, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 32/57] kvm-irqchip: x86: add msi route notify fn, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 31/57] kvm-irqchip: i386: add hook for add/remove virq, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 33/57] kvm-irqchip: do explicit commit when update irq, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 34/57] intel_iommu: support all masks in interrupt entry cache invalidation, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 35/57] kvm-all: add trace events for kvm irqchip ops, Michael S. Tsirkin, 2016/07/21
[Qemu-devel] [PULL v5 36/57] intel_iommu: disallow kernel-irqchip=on with IR, Michael S. Tsirkin, 2016/07/21