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[Qemu-devel] [PULL 60/66] ppc: Don't generate dead code on unconditional
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 60/66] ppc: Don't generate dead code on unconditional branches |
Date: |
Tue, 6 Sep 2016 13:40:47 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
We are always generating the "else" case of the condition even when
generating an unconditional branch that will never hit it.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 0a5a3e2..618334a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3480,8 +3480,10 @@ static inline void gen_bcond(DisasContext *ctx, int type)
} else {
gen_goto_tb(ctx, 0, li);
}
- gen_set_label(l1);
- gen_goto_tb(ctx, 1, ctx->nip);
+ if ((bo & 0x14) != 0x14) {
+ gen_set_label(l1);
+ gen_goto_tb(ctx, 1, ctx->nip);
+ }
} else {
if (NARROW_MODE(ctx)) {
tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
@@ -3489,9 +3491,11 @@ static inline void gen_bcond(DisasContext *ctx, int type)
tcg_gen_andi_tl(cpu_nip, target, ~3);
}
tcg_gen_exit_tb(0);
- gen_set_label(l1);
- gen_update_nip(ctx, ctx->nip);
- tcg_gen_exit_tb(0);
+ if ((bo & 0x14) != 0x14) {
+ gen_set_label(l1);
+ gen_update_nip(ctx, ctx->nip);
+ tcg_gen_exit_tb(0);
+ }
}
if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
tcg_temp_free(target);
--
2.7.4
- [Qemu-devel] [PULL 36/66] ppc: Don't update NIP if not taking alignment exceptions, (continued)
- [Qemu-devel] [PULL 36/66] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 31/66] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 23/66] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 28/66] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 38/66] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 19/66] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 03/66] target-ppc: Introduce Power9 family, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 26/66] ppc: FP exceptions are always precise, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 25/66] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 45/66] ppc: Speed up load/store multiple, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 60/66] ppc: Don't generate dead code on unconditional branches,
David Gibson <=
- [Qemu-devel] [PULL 42/66] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 49/66] target-ppc: add vabsdu[b, h, w] instructions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 46/66] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/05
- [Qemu-devel] [PULL 32/66] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 51/66] target-ppc: add vslv instruction, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 43/66] ppc: Use a helper to generate "LE unsupported" alignment interrupts, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 41/66] ppc: Fix CFAR updates, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 48/66] target-ppc: add dtstsfi[q] instructions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 44/66] ppc: load/store multiple and string insns don't do LE, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 63/66] ppc: Improve a few more helper flags, David Gibson, 2016/09/05