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[Qemu-devel] [PULL 34/64] ppc: Don't update NIP on conditional trap inst
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 34/64] ppc: Don't update NIP on conditional trap instructions |
Date: |
Wed, 7 Sep 2016 20:29:13 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This is no longer necessary as the helpers will properly retrieve
the return address when needed.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/excp_helper.c | 6 ++++--
target-ppc/translate.c | 8 --------
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index d31eece..882d529 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -1031,7 +1031,8 @@ void helper_tw(CPUPPCState *env, target_ulong arg1,
target_ulong arg2,
((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
- raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_TRAP, GETPC());
}
}
@@ -1044,7 +1045,8 @@ void helper_td(CPUPPCState *env, target_ulong arg1,
target_ulong arg2,
((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01))))) {
- raise_exception_err(env, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_TRAP, GETPC());
}
}
#endif
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f75cdc6..93cd98c 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3580,8 +3580,6 @@ static void gen_sc(DisasContext *ctx)
static void gen_tw(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3592,8 +3590,6 @@ static void gen_twi(DisasContext *ctx)
{
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
@@ -3604,8 +3600,6 @@ static void gen_twi(DisasContext *ctx)
static void gen_td(DisasContext *ctx)
{
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
t0);
tcg_temp_free_i32(t0);
@@ -3616,8 +3610,6 @@ static void gen_tdi(DisasContext *ctx)
{
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
- /* Update the nip since this might generate a trap exception */
- gen_update_nip(ctx, ctx->nip - 4);
gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
tcg_temp_free(t0);
tcg_temp_free_i32(t1);
--
2.7.4
- [Qemu-devel] [PULL 03/64] target-ppc: Introduce Power9 family, (continued)
- [Qemu-devel] [PULL 03/64] target-ppc: Introduce Power9 family, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 04/64] target-ppc: Introduce POWER ISA 3.0 flag, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 07/64] target-ppc: add modulo word operations, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 02/64] hw/ppc: include fdt helper routine in a common file, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 10/64] target-ppc: add cnttzw[.] instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 11/64] target-ppc: add cmpeqb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 06/64] target-ppc: add cmprb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 32/64] ppc: Don't update NIP in facility unavailable interrupts, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 08/64] target-ppc: add modulo dword operations, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 13/64] target-ppc: add maddld instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 34/64] ppc: Don't update NIP on conditional trap instructions,
David Gibson <=
- [Qemu-devel] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 16/64] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 30/64] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 19/64] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 28/64] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 26/64] ppc: FP exceptions are always precise, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 50/64] target-ppc: add vsrv instruction, David Gibson, 2016/09/07