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[Qemu-devel] [PULL 35/64] ppc: Don't update NIP if not taking alignment
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions |
Date: |
Wed, 7 Sep 2016 20:29:14 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Move the NIP update to after the conditional branch so that we
don't do it if we aren't going to take the alignment exception
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 93cd98c..6320ae5 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2414,12 +2414,11 @@ static inline void gen_check_align(DisasContext *ctx,
TCGv EA, int mask)
TCGLabel *l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
TCGv_i32 t1, t2;
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
tcg_gen_andi_tl(t0, EA, mask);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
t2 = tcg_const_i32(0);
+ gen_update_nip(ctx, ctx->nip - 4);
gen_helper_raise_exception_err(cpu_env, t1, t2);
tcg_temp_free_i32(t1);
tcg_temp_free_i32(t2);
--
2.7.4
- [Qemu-devel] [PULL 08/64] target-ppc: add modulo dword operations, (continued)
- [Qemu-devel] [PULL 08/64] target-ppc: add modulo dword operations, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 13/64] target-ppc: add maddld instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 34/64] ppc: Don't update NIP on conditional trap instructions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 15/64] target-ppc: introduce opc4 for Expanded Opcode, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 16/64] ppc: Provide basic raise_exception_* functions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 30/64] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 19/64] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 33/64] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 28/64] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions,
David Gibson <=
- [Qemu-devel] [PULL 26/64] ppc: FP exceptions are always precise, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 50/64] target-ppc: add vsrv instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 27/64] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 37/64] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 44/64] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/07
- [Qemu-devel] [PULL 14/64] target-ppc: add maddhd and maddhdu instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 09/64] target-ppc: add cnttzd[.] instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 25/64] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07