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[Qemu-devel] [PULL 42/64] ppc: Use a helper to generate "LE unsupported"
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 42/64] ppc: Use a helper to generate "LE unsupported" alignment interrupts |
Date: |
Wed, 7 Sep 2016 20:29:21 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Some operations aren't allowed in LE mode, use a helper rather than
open coding the exception generation.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5986435..1315656 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2427,6 +2427,12 @@ static inline void gen_check_align(DisasContext *ctx,
TCGv EA, int mask)
tcg_temp_free(t0);
}
+static inline void gen_align_no_le(DisasContext *ctx)
+{
+ gen_exception_err(ctx, POWERPC_EXCP_ALIGN,
+ (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE);
+}
+
/*** Integer load ***/
static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
@@ -2647,10 +2653,9 @@ static void gen_lq(DisasContext *ctx)
}
if (!le_is_supported && ctx->le_mode) {
- gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
+ gen_align_no_le(ctx);
return;
}
-
ra = rA(ctx->opcode);
rd = rD(ctx->opcode);
if (unlikely((rd & 1) || rd == ra)) {
@@ -2781,7 +2786,7 @@ static void gen_std(DisasContext *ctx)
}
if (!le_is_supported && ctx->le_mode) {
- gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
+ gen_align_no_le(ctx);
return;
}
--
2.7.4
- [Qemu-devel] [PULL 09/64] target-ppc: add cnttzd[.] instruction, (continued)
- [Qemu-devel] [PULL 09/64] target-ppc: add cnttzd[.] instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 25/64] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 38/64] ppc: Handle unconditional (always/never) traps at translation time, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 48/64] target-ppc: add vcmpnez[b, h, w][.] instructions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 60/64] ppc: Improve the exception helpers flags, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 54/64] hw/ppc: add a ppc_create_page_sizes_prop() helper routine, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 43/64] ppc: load/store multiple and string insns don't do LE, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 47/64] target-ppc: add vabsdu[b, h, w] instructions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 42/64] ppc: Use a helper to generate "LE unsupported" alignment interrupts,
David Gibson <=
- [Qemu-devel] [PULL 49/64] target-ppc: add vslv instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 24/64] ppc: Make float_check_status() pass the return address, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 29/64] ppc: Make tlb_fill() use new exception helper, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 51/64] target-ppc: add extswsli[.] instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 53/64] hw/ppc: use error_report instead of fprintf, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 41/64] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 39/64] ppc: Speed up dcbz, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 40/64] ppc: Fix CFAR updates, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 55/64] ppc: Fix macio ESCC legacy mapping, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 46/64] target-ppc: add dtstsfi[q] instructions, David Gibson, 2016/09/07