[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the ret
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the return address |
Date: |
Wed, 7 Sep 2016 20:29:02 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
Instead of relying on NIP having been updated already
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/fpu_helper.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index e1f600a..8d881fc 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -19,6 +19,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
#define float32_snan_to_qnan(x) ((x) | 0x00400000)
@@ -200,8 +201,9 @@ static inline uint64_t float_invalid_op_excp(CPUPPCState
*env, int op,
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
if (msr_fe0 != 0 || msr_fe1 != 0) {
- helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_FP | op);
+ /* GETPC() works here because this is inline */
+ raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_FP | op, GETPC());
}
}
return ret;
--
2.7.4
- [Qemu-devel] [PULL 12/64] target-ppc: add setb instruction, (continued)
- [Qemu-devel] [PULL 12/64] target-ppc: add setb instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 35/64] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 26/64] ppc: FP exceptions are always precise, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 50/64] target-ppc: add vsrv instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 27/64] ppc: Don't update NIP in lswi/lswx/stswi/stswx, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 37/64] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 44/64] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/07
- [Qemu-devel] [PULL 14/64] target-ppc: add maddhd and maddhdu instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 09/64] target-ppc: add cnttzd[.] instruction, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 25/64] ppc: Don't update the NIP in floating point generated code, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 23/64] ppc: Make float_invalid_op_excp() pass the return address,
David Gibson <=
- [Qemu-devel] [PULL 31/64] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 38/64] ppc: Handle unconditional (always/never) traps at translation time, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 48/64] target-ppc: add vcmpnez[b, h, w][.] instructions, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 60/64] ppc: Improve the exception helpers flags, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 54/64] hw/ppc: add a ppc_create_page_sizes_prop() helper routine, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 43/64] ppc: load/store multiple and string insns don't do LE, David Gibson, 2016/09/07
- [Qemu-devel] [PULL 47/64] target-ppc: add vabsdu[b, h, w] instructions, David Gibson, 2016/09/07