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[Qemu-devel] [PATCH RFC v1 08/29] target-arc: MOV, EXT, SEX, SWAP
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH RFC v1 08/29] target-arc: MOV, EXT, SEX, SWAP |
Date: |
Fri, 9 Sep 2016 01:31:49 +0300 |
Signed-off-by: Michael Rolnik <address@hidden>
---
target-arc/translate-inst.c | 156 ++++++++++++++++++++++++++++++++++++++++++++
target-arc/translate-inst.h | 7 ++
2 files changed, 163 insertions(+)
diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 5404f35..4d756a9 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -923,3 +923,159 @@ int arc_gen_MIN(DisasCtxt *ctx, TCGv dest, TCGv src1,
TCGv src2)
return BS_NONE;
}
+/*
+ MOV
+*/
+int arc_gen_MOV(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_mov_tl(rslt, src1);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
+/*
+ EXTB
+*/
+int arc_gen_EXTB(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_ext8u_tl(rslt, src1);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_movi_tl(cpu_Nf, 0);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
+/*
+ EXTW
+*/
+int arc_gen_EXTW(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_ext16u_tl(rslt, src1);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_movi_tl(cpu_Nf, 0);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
+/*
+ SEXB
+*/
+int arc_gen_SEXB(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_ext8s_tl(rslt, src1);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
+/*
+ SEXW
+*/
+int arc_gen_SEXW(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_ext16s_tl(rslt, src1);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
+/*
+ SWAP
+*/
+int arc_gen_SWAP(DisasCtxt *ctx, TCGv dest, TCGv src1)
+{
+ TCGv rslt = dest;
+
+ if (TCGV_EQUAL(dest, src1)) {
+ rslt = tcg_temp_new_i32();
+ }
+
+ tcg_gen_rotli_tl(rslt, src1, 16);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, rslt, ctx->zero);
+ tcg_gen_shri_tl(cpu_Nf, rslt, 31);
+ }
+
+ if (!TCGV_EQUAL(dest, rslt)) {
+ tcg_gen_mov_tl(dest, rslt);
+ tcg_temp_free_i32(rslt);
+ }
+
+ return BS_NONE;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 0dc7f4c..916d94e 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -64,3 +64,10 @@ int arc_gen_SYNC(DisasCtxt *c);
int arc_gen_MAX(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
int arc_gen_MIN(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_MOV(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_EXTB(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_EXTW(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_SEXB(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_SEXW(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_SWAP(DisasCtxt *c, TCGv dest, TCGv src1);
+
--
2.4.9 (Apple Git-60)
- Re: [Qemu-devel] [PATCH RFC v1 03/29] target-arc: SUB, SUB1, SUB2, SUB3, SBC, RSUB, CMP, (continued)
- [Qemu-devel] [PATCH RFC v1 09/29] target-arc: NEG, ABS, NOT, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 07/29] target-arc: MAX, MIN, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 01/29] target-arc: initial commit, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 06/29] target-arc: EX, LD, ST, SYNC, PREFETCH, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 05/29] target-arc: ASL(m), ASR(m), LSR(m), ROR(m), Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 08/29] target-arc: MOV, EXT, SEX, SWAP,
Michael Rolnik <=
- [Qemu-devel] [PATCH RFC v1 10/29] target-arc: POP, PUSH, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 11/29] target-arc: BCLR, BMSK, BSET, BTST, BXOR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 13/29] target-arc: NORM, NORMW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 15/29] target-arc: MUL64, MULU64, DIVAW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 12/29] target-arc: RLC, RRC, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 14/29] target-arc: MPY, MPYH, MPYHU, MPYU, Michael Rolnik, 2016/09/08