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[Qemu-devel] [PATCH RFC v1 14/29] target-arc: MPY, MPYH, MPYHU, MPYU
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH RFC v1 14/29] target-arc: MPY, MPYH, MPYHU, MPYU |
Date: |
Fri, 9 Sep 2016 01:31:55 +0300 |
Signed-off-by: Michael Rolnik <address@hidden>
---
target-arc/translate-inst.c | 129 ++++++++++++++++++++++++++++++++++++++++++++
target-arc/translate-inst.h | 5 ++
2 files changed, 134 insertions(+)
diff --git a/target-arc/translate-inst.c b/target-arc/translate-inst.c
index 00785bf..92c75ac 100644
--- a/target-arc/translate-inst.c
+++ b/target-arc/translate-inst.c
@@ -1417,3 +1417,132 @@ int arc_gen_NORM(DisasCtxt *ctx, TCGv dest, TCGv src1)
return BS_NONE;
}
+/*
+ MPY
+*/
+int arc_gen_MPY(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv_i64 rslt = tcg_temp_new_i64();
+ TCGv_i64 srcA = tcg_temp_new_i64();
+ TCGv_i64 srcB = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(srcA, src1);
+ tcg_gen_ext_i32_i64(srcB, src2);
+
+ tcg_gen_mul_i64(rslt, srcA, srcB);
+
+ tcg_gen_trunc_i64_tl(dest, rslt);
+
+ if (ctx->opt.f) {
+ TCGv_i64 temp = tcg_temp_new_i64();
+
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero);
+
+ tcg_gen_trunc_i64_tl(cpu_Nf, rslt);
+ tcg_gen_shri_tl(cpu_Nf, cpu_Nf, 31);
+
+ tcg_gen_ext_i32_i64(temp, dest);
+ tcg_gen_setcond_i64(TCG_COND_NE, temp, temp, rslt);
+ tcg_gen_trunc_i64_tl(cpu_Cf, temp);
+
+ tcg_temp_free_i64(temp);
+ }
+
+ tcg_temp_free_i64(rslt);
+ tcg_temp_free_i64(srcA);
+ tcg_temp_free_i64(srcB);
+
+ return BS_NONE;
+}
+
+/*
+ MPYH
+*/
+int arc_gen_MPYH(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv_i64 rslt = tcg_temp_new_i64();
+ TCGv_i64 srcA = tcg_temp_new_i64();
+ TCGv_i64 srcB = tcg_temp_new_i64();
+
+ tcg_gen_ext_i32_i64(srcA, src1);
+ tcg_gen_ext_i32_i64(srcB, src2);
+
+ tcg_gen_mul_i64(rslt, srcA, srcB);
+
+ tcg_gen_sari_i64(rslt, rslt, 32);
+ tcg_gen_trunc_i64_tl(dest, rslt);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero);
+ tcg_gen_shri_tl(cpu_Nf, dest, 31);
+ tcg_gen_movi_tl(cpu_Vf, 0);
+ }
+
+ tcg_temp_free_i64(rslt);
+ tcg_temp_free_i64(srcA);
+ tcg_temp_free_i64(srcB);
+
+ return BS_NONE;
+}
+
+/*
+ MPYHU
+*/
+int arc_gen_MPYHU(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv_i64 rslt = tcg_temp_new_i64();
+ TCGv_i64 srcA = tcg_temp_new_i64();
+ TCGv_i64 srcB = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(srcA, src1);
+ tcg_gen_extu_i32_i64(srcB, src2);
+
+ tcg_gen_mul_i64(rslt, srcA, srcB);
+
+ tcg_gen_shri_i64(rslt, rslt, 32);
+ tcg_gen_trunc_i64_tl(dest, rslt);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero);
+ tcg_gen_movi_tl(cpu_Nf, 0);
+ tcg_gen_movi_tl(cpu_Vf, 0);
+ }
+
+ tcg_temp_free_i64(rslt);
+ tcg_temp_free_i64(srcA);
+ tcg_temp_free_i64(srcB);
+
+ return BS_NONE;
+}
+
+/*
+ MPYU
+*/
+int arc_gen_MPYU(DisasCtxt *ctx, TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv_i64 rslt = tcg_temp_new_i64();
+ TCGv_i64 srcA = tcg_temp_new_i64();
+ TCGv_i64 srcB = tcg_temp_new_i64();
+
+ tcg_gen_extu_i32_i64(srcA, src1);
+ tcg_gen_extu_i32_i64(srcB, src2);
+
+ tcg_gen_mul_i64(rslt, srcA, srcB);
+
+ tcg_gen_trunc_i64_tl(dest, rslt);
+
+ if (ctx->opt.f) {
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_Zf, dest, ctx->zero);
+ tcg_gen_movi_tl(cpu_Nf, 0);
+ tcg_gen_shri_i64(rslt, rslt, 32);
+ tcg_gen_trunc_i64_tl(cpu_Vf, rslt);
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_Vf, cpu_Vf, 0);
+ }
+
+ tcg_temp_free_i64(rslt);
+ tcg_temp_free_i64(srcA);
+ tcg_temp_free_i64(srcB);
+
+ return BS_NONE;
+}
+
diff --git a/target-arc/translate-inst.h b/target-arc/translate-inst.h
index 811c914..084c282 100644
--- a/target-arc/translate-inst.h
+++ b/target-arc/translate-inst.h
@@ -90,3 +90,8 @@ int arc_gen_RLC(DisasCtxt *c, TCGv dest, TCGv src1);
int arc_gen_NORMW(DisasCtxt *c, TCGv dest, TCGv src1);
int arc_gen_NORM(DisasCtxt *c, TCGv dest, TCGv src1);
+int arc_gen_MPY(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_MPYH(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_MPYHU(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+int arc_gen_MPYU(DisasCtxt *c, TCGv dest, TCGv src1, TCGv src2);
+
--
2.4.9 (Apple Git-60)
- [Qemu-devel] [PATCH RFC v1 08/29] target-arc: MOV, EXT, SEX, SWAP, (continued)
- [Qemu-devel] [PATCH RFC v1 08/29] target-arc: MOV, EXT, SEX, SWAP, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 10/29] target-arc: POP, PUSH, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 11/29] target-arc: BCLR, BMSK, BSET, BTST, BXOR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 13/29] target-arc: NORM, NORMW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 15/29] target-arc: MUL64, MULU64, DIVAW, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 12/29] target-arc: RLC, RRC, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 14/29] target-arc: MPY, MPYH, MPYHU, MPYU,
Michael Rolnik <=
- [Qemu-devel] [PATCH RFC v1 16/29] target-arc: BBIT0, BBIT1, BR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 18/29] target-arc: J, JL, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 17/29] target-arc: B, BL, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 19/29] target-arc: LR, SR, Michael Rolnik, 2016/09/08
- [Qemu-devel] [PATCH RFC v1 22/29] target-arc: ASLS, ASRS, Michael Rolnik, 2016/09/08