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[Qemu-devel] [PATCH v2 05/15] target-sparc: Handle more twinx asis
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 05/15] target-sparc: Handle more twinx asis |
Date: |
Tue, 18 Oct 2016 19:34:20 -0700 |
As used by HelenOS, presumably for ultra 2 and 3,
prior to the sun4v platform and the current twinx names.
Signed-off-by: Richard Henderson <address@hidden>
---
target-sparc/translate.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 86432ac..e7e07de 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2077,12 +2077,16 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
case ASI_REAL_IO_L: /* Bypass, non-cacheable LE */
case ASI_TWINX_REAL: /* Real address, twinx */
case ASI_TWINX_REAL_L: /* Real address, twinx, LE */
+ case ASI_QUAD_LDD_PHYS:
+ case ASI_QUAD_LDD_PHYS_L:
mem_idx = MMU_PHYS_IDX;
break;
case ASI_N: /* Nucleus */
case ASI_NL: /* Nucleus LE */
case ASI_TWINX_N:
case ASI_TWINX_NL:
+ case ASI_NUCLEUS_QUAD_LDD:
+ case ASI_NUCLEUS_QUAD_LDD_L:
mem_idx = MMU_NUCLEUS_IDX;
break;
case ASI_AIUP: /* As if user primary */
@@ -2164,6 +2168,10 @@ static DisasASI get_asi(DisasContext *dc, int insn,
TCGMemOp memop)
case ASI_TWINX_PL:
case ASI_TWINX_S:
case ASI_TWINX_SL:
+ case ASI_QUAD_LDD_PHYS:
+ case ASI_QUAD_LDD_PHYS_L:
+ case ASI_NUCLEUS_QUAD_LDD:
+ case ASI_NUCLEUS_QUAD_LDD_L:
type = GET_ASI_DTWINX;
break;
case ASI_BLK_COMMIT_P:
--
2.7.4
- [Qemu-devel] [PATCH v2 00/15] target-sparc improvements, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 01/15] target-sparc: Use overalignment flags for twinx and block asis, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 03/15] target-sparc: Add MMU_PHYS_IDX, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 05/15] target-sparc: Handle more twinx asis,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 02/15] target-sparc: Introduce cpu_raise_exception_ra, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 04/15] target-sparc: Use MMU_PHYS_IDX for bypass asis, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 06/15] target-sparc: Implement swap_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 07/15] target-sparc: Implement ldstub_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 09/15] target-sparc: Implement BCOPY/BFILL inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 08/15] target-sparc: Implement cas_asi/casx_asi inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 12/15] target-sparc: Allow 4-byte alignment on fp mem ops, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 15/15] target-sparc: Use tcg_gen_atomic_cmpxchg_tl, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 10/15] target-sparc: Remove asi helper code handled inline, Richard Henderson, 2016/10/18
- [Qemu-devel] [PATCH v2 13/15] target-sparc: Remove MMU_MODE*_SUFFIX, Richard Henderson, 2016/10/18